Lines Matching defs:reg_ch_base
90 void __iomem *reg_ch_base;
170 writel(val, xc->reg_ch_base + XDMAC_TFA);
173 writel(lower_32_bits(src_addr), xc->reg_ch_base + XDMAC_SAD);
174 writel(upper_32_bits(src_addr), xc->reg_ch_base + XDMAC_EXSAD);
176 writel(lower_32_bits(dst_addr), xc->reg_ch_base + XDMAC_DAD);
177 writel(upper_32_bits(dst_addr), xc->reg_ch_base + XDMAC_EXDAD);
181 writel(src_mode, xc->reg_ch_base + XDMAC_SADM);
182 writel(dst_mode, xc->reg_ch_base + XDMAC_DADM);
184 writel(its, xc->reg_ch_base + XDMAC_ITS);
185 writel(tnum, xc->reg_ch_base + XDMAC_TNUM);
189 xc->reg_ch_base + XDMAC_IEN);
192 val = readl(xc->reg_ch_base + XDMAC_TSS);
194 writel(val, xc->reg_ch_base + XDMAC_TSS);
203 val = readl(xc->reg_ch_base + XDMAC_IEN);
205 writel(val, xc->reg_ch_base + XDMAC_IEN);
208 val = readl(xc->reg_ch_base + XDMAC_TSS);
210 writel(0, xc->reg_ch_base + XDMAC_TSS);
213 return readl_poll_timeout_atomic(xc->reg_ch_base + XDMAC_STAT, val,
237 stat = readl(xc->reg_ch_base + XDMAC_ID);
259 writel(stat, xc->reg_ch_base + XDMAC_IR);
460 xc->reg_ch_base = xdev->reg_base + XDMAC_CH_WIDTH * ch;