Lines Matching refs:tr_req
2882 struct cppi5_tr_type1_t *tr_req = NULL;
2911 tr_req = d->hwdesc[0].tr_req_base;
2925 cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1, false,
2927 cppi5_tr_csf_set(&tr_req[tr_idx].flags, CPPI5_TR_CSF_SUPR_EVT);
2930 tr_req[tr_idx].addr = sg_addr;
2931 tr_req[tr_idx].icnt0 = tr0_cnt0;
2932 tr_req[tr_idx].icnt1 = tr0_cnt1;
2933 tr_req[tr_idx].dim1 = tr0_cnt0;
2937 cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1,
2940 cppi5_tr_csf_set(&tr_req[tr_idx].flags,
2943 tr_req[tr_idx].addr = sg_addr + tr0_cnt1 * tr0_cnt0;
2944 tr_req[tr_idx].icnt0 = tr1_cnt0;
2945 tr_req[tr_idx].icnt1 = 1;
2946 tr_req[tr_idx].dim1 = tr1_cnt0;
2953 cppi5_tr_csf_set(&tr_req[tr_idx - 1].flags,
2966 struct cppi5_tr_type15_t *tr_req = NULL;
3045 tr_req = d->hwdesc[0].tr_req_base;
3061 cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE15, false,
3063 cppi5_tr_csf_set(&tr_req[tr_idx].flags, csf);
3064 cppi5_tr_set_trigger(&tr_req[tr_idx].flags,
3070 tr_req[tr_idx].addr = dev_addr;
3071 tr_req[tr_idx].icnt0 = tr_cnt0;
3072 tr_req[tr_idx].icnt1 = tr_cnt1;
3073 tr_req[tr_idx].icnt2 = tr0_cnt2;
3074 tr_req[tr_idx].icnt3 = tr0_cnt3;
3075 tr_req[tr_idx].dim1 = (-1) * tr_cnt0;
3077 tr_req[tr_idx].daddr = sg_addr;
3078 tr_req[tr_idx].dicnt0 = tr_cnt0;
3079 tr_req[tr_idx].dicnt1 = tr_cnt1;
3080 tr_req[tr_idx].dicnt2 = tr0_cnt2;
3081 tr_req[tr_idx].dicnt3 = tr0_cnt3;
3082 tr_req[tr_idx].ddim1 = tr_cnt0;
3083 tr_req[tr_idx].ddim2 = trigger_size;
3084 tr_req[tr_idx].ddim3 = trigger_size * tr0_cnt2;
3086 tr_req[tr_idx].addr = sg_addr;
3087 tr_req[tr_idx].icnt0 = tr_cnt0;
3088 tr_req[tr_idx].icnt1 = tr_cnt1;
3089 tr_req[tr_idx].icnt2 = tr0_cnt2;
3090 tr_req[tr_idx].icnt3 = tr0_cnt3;
3091 tr_req[tr_idx].dim1 = tr_cnt0;
3092 tr_req[tr_idx].dim2 = trigger_size;
3093 tr_req[tr_idx].dim3 = trigger_size * tr0_cnt2;
3095 tr_req[tr_idx].daddr = dev_addr;
3096 tr_req[tr_idx].dicnt0 = tr_cnt0;
3097 tr_req[tr_idx].dicnt1 = tr_cnt1;
3098 tr_req[tr_idx].dicnt2 = tr0_cnt2;
3099 tr_req[tr_idx].dicnt3 = tr0_cnt3;
3100 tr_req[tr_idx].ddim1 = (-1) * tr_cnt0;
3106 cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE15,
3109 cppi5_tr_csf_set(&tr_req[tr_idx].flags, csf);
3110 cppi5_tr_set_trigger(&tr_req[tr_idx].flags,
3117 tr_req[tr_idx].addr = dev_addr;
3118 tr_req[tr_idx].icnt0 = tr_cnt0;
3119 tr_req[tr_idx].icnt1 = tr_cnt1;
3120 tr_req[tr_idx].icnt2 = tr1_cnt2;
3121 tr_req[tr_idx].icnt3 = 1;
3122 tr_req[tr_idx].dim1 = (-1) * tr_cnt0;
3124 tr_req[tr_idx].daddr = sg_addr;
3125 tr_req[tr_idx].dicnt0 = tr_cnt0;
3126 tr_req[tr_idx].dicnt1 = tr_cnt1;
3127 tr_req[tr_idx].dicnt2 = tr1_cnt2;
3128 tr_req[tr_idx].dicnt3 = 1;
3129 tr_req[tr_idx].ddim1 = tr_cnt0;
3130 tr_req[tr_idx].ddim2 = trigger_size;
3132 tr_req[tr_idx].addr = sg_addr;
3133 tr_req[tr_idx].icnt0 = tr_cnt0;
3134 tr_req[tr_idx].icnt1 = tr_cnt1;
3135 tr_req[tr_idx].icnt2 = tr1_cnt2;
3136 tr_req[tr_idx].icnt3 = 1;
3137 tr_req[tr_idx].dim1 = tr_cnt0;
3138 tr_req[tr_idx].dim2 = trigger_size;
3140 tr_req[tr_idx].daddr = dev_addr;
3141 tr_req[tr_idx].dicnt0 = tr_cnt0;
3142 tr_req[tr_idx].dicnt1 = tr_cnt1;
3143 tr_req[tr_idx].dicnt2 = tr1_cnt2;
3144 tr_req[tr_idx].dicnt3 = 1;
3145 tr_req[tr_idx].ddim1 = (-1) * tr_cnt0;
3153 cppi5_tr_csf_set(&tr_req[tr_idx - 1].flags, csf | CPPI5_TR_CSF_EOP);
3474 struct cppi5_tr_type1_t *tr_req;
3494 tr_req = d->hwdesc[0].tr_req_base;
3504 cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1, false,
3507 tr_req[tr_idx].addr = period_addr;
3508 tr_req[tr_idx].icnt0 = tr0_cnt0;
3509 tr_req[tr_idx].icnt1 = tr0_cnt1;
3510 tr_req[tr_idx].dim1 = tr0_cnt0;
3513 cppi5_tr_csf_set(&tr_req[tr_idx].flags,
3517 cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1,
3521 tr_req[tr_idx].addr = period_addr + tr0_cnt1 * tr0_cnt0;
3522 tr_req[tr_idx].icnt0 = tr1_cnt0;
3523 tr_req[tr_idx].icnt1 = 1;
3524 tr_req[tr_idx].dim1 = tr1_cnt0;
3528 cppi5_tr_csf_set(&tr_req[tr_idx].flags,
3678 struct cppi5_tr_type15_t *tr_req;
3717 tr_req = d->hwdesc[0].tr_req_base;
3719 cppi5_tr_init(&tr_req[0].flags, CPPI5_TR_TYPE15, false, true,
3721 cppi5_tr_csf_set(&tr_req[0].flags, csf);
3723 tr_req[0].addr = src;
3724 tr_req[0].icnt0 = tr0_cnt0;
3725 tr_req[0].icnt1 = tr0_cnt1;
3726 tr_req[0].icnt2 = 1;
3727 tr_req[0].icnt3 = 1;
3728 tr_req[0].dim1 = tr0_cnt0;
3730 tr_req[0].daddr = dest;
3731 tr_req[0].dicnt0 = tr0_cnt0;
3732 tr_req[0].dicnt1 = tr0_cnt1;
3733 tr_req[0].dicnt2 = 1;
3734 tr_req[0].dicnt3 = 1;
3735 tr_req[0].ddim1 = tr0_cnt0;
3738 cppi5_tr_init(&tr_req[1].flags, CPPI5_TR_TYPE15, false, true,
3740 cppi5_tr_csf_set(&tr_req[1].flags, csf);
3742 tr_req[1].addr = src + tr0_cnt1 * tr0_cnt0;
3743 tr_req[1].icnt0 = tr1_cnt0;
3744 tr_req[1].icnt1 = 1;
3745 tr_req[1].icnt2 = 1;
3746 tr_req[1].icnt3 = 1;
3748 tr_req[1].daddr = dest + tr0_cnt1 * tr0_cnt0;
3749 tr_req[1].dicnt0 = tr1_cnt0;
3750 tr_req[1].dicnt1 = 1;
3751 tr_req[1].dicnt2 = 1;
3752 tr_req[1].dicnt3 = 1;
3755 cppi5_tr_csf_set(&tr_req[num_tr - 1].flags, csf | CPPI5_TR_CSF_EOP);
5114 struct cppi5_tr_type1_t *tr_req;
5161 tr_req = hwdesc->tr_req_base;
5162 cppi5_tr_init(&tr_req->flags, CPPI5_TR_TYPE1, false, false,
5164 cppi5_tr_csf_set(&tr_req->flags, CPPI5_TR_CSF_SUPR_EVT);
5166 tr_req->addr = rx_flush->buffer_paddr;
5167 tr_req->icnt0 = rx_flush->buffer_size;
5168 tr_req->icnt1 = 1;