Lines Matching refs:echan
177 struct edma_chan *echan;
390 static void edma_set_chmap(struct edma_chan *echan, int slot)
392 struct edma_cc *ecc = echan->ecc;
393 int channel = EDMA_CHAN_SLOT(echan->ch_num);
401 static void edma_setup_interrupt(struct edma_chan *echan, bool enable)
403 struct edma_cc *ecc = echan->ecc;
404 int channel = EDMA_CHAN_SLOT(echan->ch_num);
546 static void edma_start(struct edma_chan *echan)
548 struct edma_cc *ecc = echan->ecc;
549 int channel = EDMA_CHAN_SLOT(echan->ch_num);
553 if (!echan->hw_triggered) {
573 static void edma_stop(struct edma_chan *echan)
575 struct edma_cc *ecc = echan->ecc;
576 int channel = EDMA_CHAN_SLOT(echan->ch_num);
600 static void edma_pause(struct edma_chan *echan)
602 int channel = EDMA_CHAN_SLOT(echan->ch_num);
604 edma_shadow0_write_array(echan->ecc, SH_EECR,
610 static void edma_resume(struct edma_chan *echan)
612 int channel = EDMA_CHAN_SLOT(echan->ch_num);
614 edma_shadow0_write_array(echan->ecc, SH_EESR,
619 static void edma_trigger_channel(struct edma_chan *echan)
621 struct edma_cc *ecc = echan->ecc;
622 int channel = EDMA_CHAN_SLOT(echan->ch_num);
632 static void edma_clean_channel(struct edma_chan *echan)
634 struct edma_cc *ecc = echan->ecc;
635 int channel = EDMA_CHAN_SLOT(echan->ch_num);
650 static void edma_assign_channel_eventq(struct edma_chan *echan,
653 struct edma_cc *ecc = echan->ecc;
654 int channel = EDMA_CHAN_SLOT(echan->ch_num);
668 static int edma_alloc_channel(struct edma_chan *echan,
671 struct edma_cc *ecc = echan->ecc;
672 int channel = EDMA_CHAN_SLOT(echan->ch_num);
674 if (!test_bit(echan->ch_num, ecc->channels_mask)) {
676 echan->ch_num);
685 edma_stop(echan);
687 edma_setup_interrupt(echan, true);
689 edma_assign_channel_eventq(echan, eventq_no);
694 static void edma_free_channel(struct edma_chan *echan)
697 edma_stop(echan);
699 edma_setup_interrupt(echan, false);
718 static void edma_execute(struct edma_chan *echan)
720 struct edma_cc *ecc = echan->ecc;
723 struct device *dev = echan->vchan.chan.device->dev;
726 if (!echan->edesc) {
728 vdesc = vchan_next_desc(&echan->vchan);
732 echan->edesc = to_edma_desc(&vdesc->tx);
735 edesc = echan->edesc;
745 edma_write_slot(ecc, echan->slot[i], &edesc->pset[j].param);
759 j, echan->ch_num, echan->slot[i],
770 edma_link(ecc, echan->slot[i], echan->slot[i + 1]);
782 edma_link(ecc, echan->slot[nslots - 1], echan->slot[1]);
784 edma_link(ecc, echan->slot[nslots - 1],
785 echan->ecc->dummy_slot);
788 if (echan->missed) {
794 dev_dbg(dev, "missed event on channel %d\n", echan->ch_num);
795 edma_clean_channel(echan);
796 edma_stop(echan);
797 edma_start(echan);
798 edma_trigger_channel(echan);
799 echan->missed = 0;
802 echan->ch_num);
803 edma_start(echan);
806 echan->ch_num, edesc->processed);
807 edma_resume(echan);
813 struct edma_chan *echan = to_edma_chan(chan);
817 spin_lock_irqsave(&echan->vchan.lock, flags);
822 * echan->edesc is NULL and exit.)
824 if (echan->edesc) {
825 edma_stop(echan);
827 if (!echan->tc && echan->edesc->cyclic)
828 edma_assign_channel_eventq(echan, EVENTQ_DEFAULT);
830 vchan_terminate_vdesc(&echan->edesc->vdesc);
831 echan->edesc = NULL;
834 vchan_get_all_descriptors(&echan->vchan, &head);
835 spin_unlock_irqrestore(&echan->vchan.lock, flags);
836 vchan_dma_desc_free_list(&echan->vchan, &head);
843 struct edma_chan *echan = to_edma_chan(chan);
845 vchan_synchronize(&echan->vchan);
851 struct edma_chan *echan = to_edma_chan(chan);
861 memcpy(&echan->cfg, cfg, sizeof(echan->cfg));
868 struct edma_chan *echan = to_edma_chan(chan);
870 if (!echan->edesc)
873 edma_pause(echan);
879 struct edma_chan *echan = to_edma_chan(chan);
881 edma_resume(echan);
901 struct edma_chan *echan = to_edma_chan(chan);
986 param->opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
1014 struct edma_chan *echan = to_edma_chan(chan);
1023 if (unlikely(!echan || !sgl || !sg_len))
1027 src_addr = echan->cfg.src_addr;
1028 dev_width = echan->cfg.src_addr_width;
1029 burst = echan->cfg.src_maxburst;
1031 dst_addr = echan->cfg.dst_addr;
1032 dev_width = echan->cfg.dst_addr_width;
1033 burst = echan->cfg.dst_maxburst;
1051 edesc->echan = echan;
1057 if (echan->slot[i] < 0) {
1058 echan->slot[i] =
1059 edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY);
1060 if (echan->slot[i] < 0) {
1102 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
1112 struct edma_chan *echan = to_edma_chan(chan);
1115 if (unlikely(!echan || !len))
1168 edesc->echan = echan;
1188 if (echan->slot[1] < 0) {
1189 echan->slot[1] = edma_alloc_slot(echan->ecc,
1191 if (echan->slot[1] < 0) {
1218 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
1227 struct edma_chan *echan = to_edma_chan(chan);
1273 edesc->echan = echan;
1285 param->opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
1293 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
1301 struct edma_chan *echan = to_edma_chan(chan);
1310 if (unlikely(!echan || !buf_len || !period_len))
1314 src_addr = echan->cfg.src_addr;
1316 dev_width = echan->cfg.src_addr_width;
1317 burst = echan->cfg.src_maxburst;
1320 dst_addr = echan->cfg.dst_addr;
1321 dev_width = echan->cfg.dst_addr_width;
1322 burst = echan->cfg.dst_maxburst;
1372 edesc->echan = echan;
1375 __func__, echan->ch_num, nslots, period_len, buf_len);
1379 if (echan->slot[i] < 0) {
1380 echan->slot[i] =
1381 edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY);
1382 if (echan->slot[i] < 0) {
1422 i, echan->ch_num, echan->slot[i],
1447 if (!echan->tc)
1448 edma_assign_channel_eventq(echan, EVENTQ_0);
1450 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
1453 static void edma_completion_handler(struct edma_chan *echan)
1455 struct device *dev = echan->vchan.chan.device->dev;
1458 spin_lock(&echan->vchan.lock);
1459 edesc = echan->edesc;
1463 spin_unlock(&echan->vchan.lock);
1467 edma_stop(echan);
1469 echan->edesc = NULL;
1472 echan->ch_num);
1475 echan->ch_num);
1477 edma_pause(echan);
1484 edma_execute(echan);
1487 spin_unlock(&echan->vchan.lock);
1536 static void edma_error_handler(struct edma_chan *echan)
1538 struct edma_cc *ecc = echan->ecc;
1539 struct device *dev = echan->vchan.chan.device->dev;
1543 if (!echan->edesc)
1546 spin_lock(&echan->vchan.lock);
1548 err = edma_read_slot(ecc, echan->slot[0], &p);
1564 echan->missed = 1;
1571 edma_clean_channel(echan);
1572 edma_stop(echan);
1573 edma_start(echan);
1574 edma_trigger_channel(echan);
1576 spin_unlock(&echan->vchan.lock);
1667 struct edma_chan *echan = to_edma_chan(chan);
1668 struct edma_cc *ecc = echan->ecc;
1673 if (echan->tc) {
1674 eventq_no = echan->tc->id;
1677 echan->tc = &ecc->tc_list[ecc->info->default_queue];
1678 eventq_no = echan->tc->id;
1681 ret = edma_alloc_channel(echan, eventq_no);
1685 echan->slot[0] = edma_alloc_slot(ecc, echan->ch_num);
1686 if (echan->slot[0] < 0) {
1688 EDMA_CHAN_SLOT(echan->ch_num));
1689 ret = echan->slot[0];
1694 edma_set_chmap(echan, echan->slot[0]);
1695 echan->alloced = true;
1698 EDMA_CHAN_SLOT(echan->ch_num), chan->chan_id,
1699 echan->hw_triggered ? "HW" : "SW");
1704 edma_free_channel(echan);
1711 struct edma_chan *echan = to_edma_chan(chan);
1712 struct device *dev = echan->ecc->dev;
1716 edma_stop(echan);
1718 vchan_free_chan_resources(&echan->vchan);
1722 if (echan->slot[i] >= 0) {
1723 edma_free_slot(echan->ecc, echan->slot[i]);
1724 echan->slot[i] = -1;
1729 edma_set_chmap(echan, echan->ecc->dummy_slot);
1732 if (echan->alloced) {
1733 edma_free_channel(echan);
1734 echan->alloced = false;
1737 echan->tc = NULL;
1738 echan->hw_triggered = false;
1741 EDMA_CHAN_SLOT(echan->ch_num), chan->chan_id);
1747 struct edma_chan *echan = to_edma_chan(chan);
1750 spin_lock_irqsave(&echan->vchan.lock, flags);
1751 if (vchan_issue_pending(&echan->vchan) && !echan->edesc)
1752 edma_execute(echan);
1753 spin_unlock_irqrestore(&echan->vchan.lock, flags);
1769 struct edma_chan *echan = edesc->echan;
1772 int channel = EDMA_CHAN_SLOT(echan->ch_num);
1782 pos = edma_get_position(echan->ecc, echan->slot[0], dst);
1798 while (edma_shadow0_read_array(echan->ecc, event_reg, idx) & ch_bit) {
1799 pos = edma_get_position(echan->ecc, echan->slot[0], dst);
1804 dev_dbg_ratelimited(echan->vchan.chan.device->dev,
1859 struct edma_chan *echan = to_edma_chan(chan);
1873 spin_lock_irqsave(&echan->vchan.lock, flags);
1874 if (echan->edesc && echan->edesc->vdesc.tx.cookie == cookie) {
1875 txstate->residue = edma_residue(echan->edesc);
1877 struct virt_dma_desc *vdesc = vchan_find_desc(&echan->vchan,
1891 echan->edesc && echan->edesc->polled &&
1892 echan->edesc->vdesc.tx.cookie == cookie) {
1893 edma_stop(echan);
1894 vchan_cookie_complete(&echan->edesc->vdesc);
1895 echan->edesc = NULL;
1896 edma_execute(echan);
1900 spin_unlock_irqrestore(&echan->vchan.lock, flags);
2002 struct edma_chan *echan = &ecc->slave_chans[i];
2003 echan->ch_num = EDMA_CTLR_CHAN(ecc->id, i);
2004 echan->ecc = ecc;
2005 echan->vchan.desc_free = edma_desc_free;
2008 vchan_init(&echan->vchan, m_ddev);
2010 vchan_init(&echan->vchan, s_ddev);
2012 INIT_LIST_HEAD(&echan->node);
2014 echan->slot[j] = -1;
2234 struct edma_chan *echan;
2241 echan = &ecc->slave_chans[i];
2242 if (echan->ch_num == dma_spec->args[0]) {
2243 chan = &echan->vchan.chan;
2251 if (echan->ecc->legacy_mode && dma_spec->args_count == 1)
2254 if (!echan->ecc->legacy_mode && dma_spec->args_count == 2 &&
2255 dma_spec->args[1] < echan->ecc->num_tc) {
2256 echan->tc = &echan->ecc->tc_list[dma_spec->args[1]];
2263 echan->hw_triggered = true;
2554 struct edma_chan *echan, *_echan;
2556 list_for_each_entry_safe(echan, _echan,
2558 list_del(&echan->vchan.chan.device_node);
2559 tasklet_kill(&echan->vchan.task);
2589 struct edma_chan *echan = ecc->slave_chans;
2593 if (echan[i].alloced)
2594 edma_setup_interrupt(&echan[i], false);
2603 struct edma_chan *echan = ecc->slave_chans;
2618 if (echan[i].alloced) {
2624 edma_setup_interrupt(&echan[i], true);
2627 edma_set_chmap(&echan[i], echan[i].slot[0]);
2668 struct edma_chan *echan = to_edma_chan(chan);
2670 if (ch_req == echan->ch_num) {
2672 echan->hw_triggered = true;