Lines Matching defs:and
42 /* Offsets for EDMA CC global channel registers and their shadows */
114 * fail. Today davinci-pcm is the only user of this driver and
185 * during edma_callback and is always <= processed, because processed
257 * and Linux must not touch it.
310 static inline void edma_modify(struct edma_cc *ecc, int offset, unsigned and,
315 val &= and;
341 unsigned and, unsigned or)
343 edma_modify(ecc, offset + (i << 2), and, or);
377 int param_no, unsigned and, unsigned or)
379 edma_modify(ecc, EDMA_PARM + offset + (param_no << 5), and, or);
446 * mapped to a hardware DMA channel, and will normally be used by
542 * events, and channels without such associations will be triggered by
778 * events being absorbed and that's OK because we're done
822 * echan->edesc is NULL and exit.)
888 * @pset: PaRAM set to initialize and setup.
918 * For the A-sync case, bcnt and ccnt are the remainder
919 * and quotient respectively of the division of:
933 * If bcnt is non-zero, we have a remainder and hence an
945 * address_width and B count is the maxburst. In this
1001 * A-sync case, and in this case, a requirement of reload value
1003 * and then later will be populated by edma_execute.
1134 * slot and with one burst.
1344 * such as Slave SGs, such delays are tolerable and synchronized,
1345 * but the synchronization is difficult to achieve with Cyclic and
1350 * If the burst and period sizes are the same, we can put
1351 * the full buffer into a single period and activate
1553 * (1) we finished transmitting an intermediate slot and
1555 * (2) or we finished current transfer and issue will
1558 * Important note: issuing can be dangerous here and
1560 * slot. So we avoid doing so and set the missed flag.
1788 * 1. while and event is pending for the channel
1841 * this is the active one. Get the current delta and
1847 /* Otherwise mark it done and update residue_stat. */
2064 * priority. So Q0 is the highest priority queue and the last queue has
2502 /* Init the dma device and channels */