Lines Matching defs:tdma
188 struct tegra_dma *tdma;
230 static inline void tdma_write(struct tegra_dma *tdma, u32 reg, u32 val)
232 writel(val, tdma->base_addr + reg);
348 struct tegra_dma *tdma = tdc->tdma;
350 spin_lock(&tdma->global_lock);
352 if (tdc->tdma->global_pause_count == 0) {
353 tdma_write(tdma, TEGRA_APBDMA_GENERAL, 0);
358 tdc->tdma->global_pause_count++;
360 spin_unlock(&tdma->global_lock);
365 struct tegra_dma *tdma = tdc->tdma;
367 spin_lock(&tdma->global_lock);
369 if (WARN_ON(tdc->tdma->global_pause_count == 0))
372 if (--tdc->tdma->global_pause_count == 0)
373 tdma_write(tdma, TEGRA_APBDMA_GENERAL,
377 spin_unlock(&tdma->global_lock);
383 struct tegra_dma *tdma = tdc->tdma;
385 if (tdma->chip_data->support_channel_pause) {
397 struct tegra_dma *tdma = tdc->tdma;
399 if (tdma->chip_data->support_channel_pause)
437 if (tdc->tdma->chip_data->support_separate_wcount_reg)
478 if (tdc->tdma->chip_data->support_separate_wcount_reg)
557 pm_runtime_put(tdc->tdma->dev);
597 pm_runtime_put(tdc->tdma->dev);
714 err = pm_runtime_resume_and_get(tdc->tdma->dev);
759 if (tdc->tdma->chip_data->support_separate_wcount_reg)
775 pm_runtime_put(tdc->tdma->dev);
809 err = pm_runtime_resume_and_get(tdc->tdma->dev);
824 pm_runtime_put(tdc->tdma->dev);
835 if (tdc->tdma->chip_data->support_separate_wcount_reg)
840 if (!tdc->tdma->chip_data->support_separate_wcount_reg)
1028 if (tdc->tdma->chip_data->support_separate_wcount_reg)
1108 len > tdc->tdma->chip_data->max_dma_count) {
1208 len > tdc->tdma->chip_data->max_dma_count) {
1348 struct tegra_dma *tdma = ofdma->of_dma_data;
1353 dev_err(tdma->dev, "Invalid slave id: %d\n", dma_spec->args[0]);
1357 chan = dma_get_any_slave_channel(&tdma->dma_dev);
1403 static int tegra_dma_init_hw(struct tegra_dma *tdma)
1407 err = reset_control_assert(tdma->rst);
1409 dev_err(tdma->dev, "failed to assert reset: %d\n", err);
1413 err = clk_enable(tdma->dma_clk);
1415 dev_err(tdma->dev, "failed to enable clk: %d\n", err);
1421 reset_control_deassert(tdma->rst);
1424 tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);
1425 tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
1426 tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFF);
1428 clk_disable(tdma->dma_clk);
1436 struct tegra_dma *tdma;
1442 size = struct_size(tdma, channels, cdata->nr_channels);
1444 tdma = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
1445 if (!tdma)
1448 tdma->dev = &pdev->dev;
1449 tdma->chip_data = cdata;
1450 platform_set_drvdata(pdev, tdma);
1452 tdma->base_addr = devm_platform_ioremap_resource(pdev, 0);
1453 if (IS_ERR(tdma->base_addr))
1454 return PTR_ERR(tdma->base_addr);
1456 tdma->dma_clk = devm_clk_get(&pdev->dev, NULL);
1457 if (IS_ERR(tdma->dma_clk)) {
1459 return PTR_ERR(tdma->dma_clk);
1462 tdma->rst = devm_reset_control_get(&pdev->dev, "dma");
1463 if (IS_ERR(tdma->rst)) {
1465 return PTR_ERR(tdma->rst);
1468 spin_lock_init(&tdma->global_lock);
1470 ret = clk_prepare(tdma->dma_clk);
1474 ret = tegra_dma_init_hw(tdma);
1481 INIT_LIST_HEAD(&tdma->dma_dev.channels);
1483 struct tegra_dma_channel *tdc = &tdma->channels[i];
1486 tdc->chan_addr = tdma->base_addr +
1506 tdc->dma_chan.device = &tdma->dma_dev;
1509 &tdma->dma_dev.channels);
1510 tdc->tdma = tdma;
1524 dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);
1525 dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);
1526 dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask);
1528 tdma->global_pause_count = 0;
1529 tdma->dma_dev.dev = &pdev->dev;
1530 tdma->dma_dev.device_alloc_chan_resources =
1532 tdma->dma_dev.device_free_chan_resources =
1534 tdma->dma_dev.device_prep_slave_sg = tegra_dma_prep_slave_sg;
1535 tdma->dma_dev.device_prep_dma_cyclic = tegra_dma_prep_dma_cyclic;
1536 tdma->dma_dev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1540 tdma->dma_dev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1544 tdma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1545 tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1546 tdma->dma_dev.device_config = tegra_dma_slave_config;
1547 tdma->dma_dev.device_terminate_all = tegra_dma_terminate_all;
1548 tdma->dma_dev.device_synchronize = tegra_dma_synchronize;
1549 tdma->dma_dev.device_tx_status = tegra_dma_tx_status;
1550 tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending;
1552 ret = dma_async_device_register(&tdma->dma_dev);
1560 tegra_dma_of_xlate, tdma);
1573 dma_async_device_unregister(&tdma->dma_dev);
1579 clk_unprepare(tdma->dma_clk);
1586 struct tegra_dma *tdma = platform_get_drvdata(pdev);
1589 dma_async_device_unregister(&tdma->dma_dev);
1591 clk_unprepare(tdma->dma_clk);
1598 struct tegra_dma *tdma = dev_get_drvdata(dev);
1600 clk_disable(tdma->dma_clk);
1607 struct tegra_dma *tdma = dev_get_drvdata(dev);
1609 return clk_enable(tdma->dma_clk);
1614 struct tegra_dma *tdma = dev_get_drvdata(dev);
1619 for (i = 0; i < tdma->chip_data->nr_channels; i++) {
1620 struct tegra_dma_channel *tdc = &tdma->channels[i];
1629 dev_err(tdma->dev, "channel %u busy\n", i);
1639 struct tegra_dma *tdma = dev_get_drvdata(dev);
1642 err = tegra_dma_init_hw(tdma);