Lines Matching defs:tdma
237 struct tegra_dma *tdma;
263 writel_relaxed(val, tdc->tdma->base_addr + tdc->chan_base_offset + reg);
268 return readl_relaxed(tdc->tdma->base_addr + tdc->chan_base_offset + reg);
311 struct tegra_dma *tdma = tdc->tdma;
319 if (test_and_set_bit(sid, &tdma->sid_m2d_reserved)) {
320 dev_err(tdma->dev, "slave id already in use\n");
325 if (test_and_set_bit(sid, &tdma->sid_d2m_reserved)) {
326 dev_err(tdma->dev, "slave id already in use\n");
341 struct tegra_dma *tdma = tdc->tdma;
346 clear_bit(sid, &tdma->sid_m2d_reserved);
349 clear_bit(sid, &tdma->sid_d2m_reserved);
384 ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr +
405 if (!tdc->tdma->chip_data->hw_support_pause)
429 if (!tdc->tdma->chip_data->hw_support_pause)
485 ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr +
554 dev_err(tdc->tdma->dev,
559 dev_err(tdc->tdma->dev,
564 dev_err(tdc->tdma->dev,
569 dev_err(tdc->tdma->dev,
574 dev_err(tdc->tdma->dev,
579 dev_err(tdc->tdma->dev,
584 dev_err(tdc->tdma->dev,
682 ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr +
708 err = tdc->tdma->chip_data->terminate(tdc);
860 unsigned int max_dma_count = tdc->tdma->chip_data->max_dma_count;
932 max_dma_count = tdc->tdma->chip_data->max_dma_count;
998 unsigned int max_dma_count = tdc->tdma->chip_data->max_dma_count;
1150 max_dma_count = tdc->tdma->chip_data->max_dma_count;
1281 struct tegra_dma *tdma = ofdma->of_dma_data;
1285 chan = dma_get_any_slave_channel(&tdma->dma_dev);
1353 struct tegra_dma *tdma;
1358 tdma = devm_kzalloc(&pdev->dev,
1359 struct_size(tdma, channels, cdata->nr_channels),
1361 if (!tdma)
1364 tdma->dev = &pdev->dev;
1365 tdma->chip_data = cdata;
1366 platform_set_drvdata(pdev, tdma);
1368 tdma->base_addr = devm_platform_ioremap_resource(pdev, 0);
1369 if (IS_ERR(tdma->base_addr))
1370 return PTR_ERR(tdma->base_addr);
1372 tdma->rst = devm_reset_control_get_exclusive(&pdev->dev, "gpcdma");
1373 if (IS_ERR(tdma->rst)) {
1374 return dev_err_probe(&pdev->dev, PTR_ERR(tdma->rst),
1377 reset_control_reset(tdma->rst);
1379 tdma->dma_dev.dev = &pdev->dev;
1389 &tdma->chan_mask);
1394 tdma->chan_mask = TEGRA_GPCDMA_DEFAULT_CHANNEL_MASK;
1397 INIT_LIST_HEAD(&tdma->dma_dev.channels);
1399 struct tegra_dma_channel *tdc = &tdma->channels[i];
1402 if (!(tdma->chan_mask & BIT(i)))
1412 tdc->tdma = tdma;
1416 vchan_init(&tdc->vc, &tdma->dma_dev);
1424 dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);
1425 dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);
1426 dma_cap_set(DMA_MEMCPY, tdma->dma_dev.cap_mask);
1427 dma_cap_set(DMA_MEMSET, tdma->dma_dev.cap_mask);
1428 dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask);
1434 tdma->dma_dev.copy_align = 2;
1435 tdma->dma_dev.fill_align = 2;
1436 tdma->dma_dev.device_alloc_chan_resources =
1438 tdma->dma_dev.device_free_chan_resources =
1440 tdma->dma_dev.device_prep_slave_sg = tegra_dma_prep_slave_sg;
1441 tdma->dma_dev.device_prep_dma_memcpy = tegra_dma_prep_dma_memcpy;
1442 tdma->dma_dev.device_prep_dma_memset = tegra_dma_prep_dma_memset;
1443 tdma->dma_dev.device_prep_dma_cyclic = tegra_dma_prep_dma_cyclic;
1444 tdma->dma_dev.device_config = tegra_dma_slave_config;
1445 tdma->dma_dev.device_terminate_all = tegra_dma_terminate_all;
1446 tdma->dma_dev.device_tx_status = tegra_dma_tx_status;
1447 tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending;
1448 tdma->dma_dev.device_pause = tegra_dma_device_pause;
1449 tdma->dma_dev.device_resume = tegra_dma_device_resume;
1450 tdma->dma_dev.device_synchronize = tegra_dma_chan_synchronize;
1451 tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1453 ret = dma_async_device_register(&tdma->dma_dev);
1461 tegra_dma_of_xlate, tdma);
1466 dma_async_device_unregister(&tdma->dma_dev);
1471 hweight_long(tdma->chan_mask));
1478 struct tegra_dma *tdma = platform_get_drvdata(pdev);
1481 dma_async_device_unregister(&tdma->dma_dev);
1488 struct tegra_dma *tdma = dev_get_drvdata(dev);
1491 for (i = 0; i < tdma->chip_data->nr_channels; i++) {
1492 struct tegra_dma_channel *tdc = &tdma->channels[i];
1494 if (!(tdma->chan_mask & BIT(i)))
1498 dev_err(tdma->dev, "channel %u busy\n", i);
1508 struct tegra_dma *tdma = dev_get_drvdata(dev);
1511 reset_control_reset(tdma->rst);
1513 for (i = 0; i < tdma->chip_data->nr_channels; i++) {
1514 struct tegra_dma_channel *tdc = &tdma->channels[i];
1516 if (!(tdma->chan_mask & BIT(i)))