Lines Matching defs:tdc
184 int (*terminate)(struct tegra_dma_channel *tdc);
223 struct tegra_dma_channel *tdc;
260 static inline void tdc_write(struct tegra_dma_channel *tdc,
263 writel_relaxed(val, tdc->tdma->base_addr + tdc->chan_base_offset + reg);
266 static inline u32 tdc_read(struct tegra_dma_channel *tdc, u32 reg)
268 return readl_relaxed(tdc->tdma->base_addr + tdc->chan_base_offset + reg);
281 static inline struct device *tdc2dev(struct tegra_dma_channel *tdc)
283 return tdc->vc.chan.device->dev;
286 static void tegra_dma_dump_chan_regs(struct tegra_dma_channel *tdc)
288 dev_dbg(tdc2dev(tdc), "DMA Channel %d name %s register dump:\n",
289 tdc->id, tdc->name);
290 dev_dbg(tdc2dev(tdc), "CSR %x STA %x CSRE %x SRC %x DST %x\n",
291 tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR),
292 tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS),
293 tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE),
294 tdc_read(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR),
295 tdc_read(tdc, TEGRA_GPCDMA_CHAN_DST_PTR)
297 dev_dbg(tdc2dev(tdc), "MCSEQ %x IOSEQ %x WCNT %x XFER %x BSTA %x\n",
298 tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ),
299 tdc_read(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ),
300 tdc_read(tdc, TEGRA_GPCDMA_CHAN_WCOUNT),
301 tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT),
302 tdc_read(tdc, TEGRA_GPCDMA_CHAN_DMA_BYTE_STATUS)
304 dev_dbg(tdc2dev(tdc), "DMA ERR_STA %x\n",
305 tdc_read(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS));
308 static int tegra_dma_sid_reserve(struct tegra_dma_channel *tdc,
311 struct tegra_dma *tdma = tdc->tdma;
312 int sid = tdc->slave_id;
334 tdc->sid_dir = direction;
339 static void tegra_dma_sid_free(struct tegra_dma_channel *tdc)
341 struct tegra_dma *tdma = tdc->tdma;
342 int sid = tdc->slave_id;
344 switch (tdc->sid_dir) {
355 tdc->sid_dir = DMA_TRANS_NONE;
366 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
368 memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig));
369 tdc->config_init = true;
374 static int tegra_dma_pause(struct tegra_dma_channel *tdc)
379 val = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE);
381 tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, val);
384 ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr +
385 tdc->chan_base_offset + TEGRA_GPCDMA_CHAN_STATUS,
392 dev_err(tdc2dev(tdc), "DMA pause timed out\n");
393 tegra_dma_dump_chan_regs(tdc);
401 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
405 if (!tdc->tdma->chip_data->hw_support_pause)
408 spin_lock_irqsave(&tdc->vc.lock, flags);
409 ret = tegra_dma_pause(tdc);
410 spin_unlock_irqrestore(&tdc->vc.lock, flags);
415 static void tegra_dma_resume(struct tegra_dma_channel *tdc)
419 val = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE);
421 tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, val);
426 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
429 if (!tdc->tdma->chip_data->hw_support_pause)
432 spin_lock_irqsave(&tdc->vc.lock, flags);
433 tegra_dma_resume(tdc);
434 spin_unlock_irqrestore(&tdc->vc.lock, flags);
439 static inline int tegra_dma_pause_noerr(struct tegra_dma_channel *tdc)
446 tegra_dma_pause(tdc);
450 static void tegra_dma_disable(struct tegra_dma_channel *tdc)
454 csr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR);
461 tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, csr);
464 status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
466 dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__);
467 tdc_write(tdc, TEGRA_GPCDMA_CHAN_STATUS, status);
471 static void tegra_dma_configure_next_sg(struct tegra_dma_channel *tdc)
473 struct tegra_dma_desc *dma_desc = tdc->dma_desc;
485 ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr +
486 tdc->chan_base_offset + TEGRA_GPCDMA_CHAN_STATUS,
495 tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_regs->wcount);
496 tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_regs->src_ptr);
497 tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_regs->dst_ptr);
498 tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR, ch_regs->high_addr_ptr);
501 tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR,
505 static void tegra_dma_start(struct tegra_dma_channel *tdc)
507 struct tegra_dma_desc *dma_desc = tdc->dma_desc;
512 vdesc = vchan_next_desc(&tdc->vc);
518 dma_desc->tdc = tdc;
519 tdc->dma_desc = dma_desc;
521 tegra_dma_resume(tdc);
526 tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_regs->wcount);
527 tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, 0);
528 tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_regs->src_ptr);
529 tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_regs->dst_ptr);
530 tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR, ch_regs->high_addr_ptr);
531 tdc_write(tdc, TEGRA_GPCDMA_CHAN_FIXED_PATTERN, ch_regs->fixed_pattern);
532 tdc_write(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ, ch_regs->mmio_seq);
533 tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, ch_regs->mc_seq);
534 tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, ch_regs->csr);
537 tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR,
541 static void tegra_dma_xfer_complete(struct tegra_dma_channel *tdc)
543 vchan_cookie_complete(&tdc->dma_desc->vd);
545 tegra_dma_sid_free(tdc);
546 tdc->dma_desc = NULL;
549 static void tegra_dma_chan_decode_error(struct tegra_dma_channel *tdc,
554 dev_err(tdc->tdma->dev,
555 "GPCDMA CH%d bm fifo full\n", tdc->id);
559 dev_err(tdc->tdma->dev,
560 "GPCDMA CH%d peripheral fifo full\n", tdc->id);
564 dev_err(tdc->tdma->dev,
565 "GPCDMA CH%d illegal peripheral id\n", tdc->id);
569 dev_err(tdc->tdma->dev,
570 "GPCDMA CH%d illegal stream id\n", tdc->id);
574 dev_err(tdc->tdma->dev,
575 "GPCDMA CH%d mc slave error\n", tdc->id);
579 dev_err(tdc->tdma->dev,
580 "GPCDMA CH%d mmio slave error\n", tdc->id);
584 dev_err(tdc->tdma->dev,
585 "GPCDMA CH%d security violation %x\n", tdc->id,
592 struct tegra_dma_channel *tdc = dev_id;
593 struct tegra_dma_desc *dma_desc = tdc->dma_desc;
598 status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS);
600 tegra_dma_chan_decode_error(tdc, status);
601 tegra_dma_dump_chan_regs(tdc);
602 tdc_write(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS, 0xFFFFFFFF);
605 spin_lock(&tdc->vc.lock);
606 status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
610 tdc_write(tdc, TEGRA_GPCDMA_CHAN_STATUS,
621 tegra_dma_configure_next_sg(tdc);
625 tegra_dma_xfer_complete(tdc);
627 tegra_dma_start(tdc);
631 spin_unlock(&tdc->vc.lock);
637 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
640 if (tdc->dma_desc)
643 spin_lock_irqsave(&tdc->vc.lock, flags);
644 if (vchan_issue_pending(&tdc->vc))
645 tegra_dma_start(tdc);
654 if (tdc->dma_desc && tdc->dma_desc->cyclic)
655 tegra_dma_configure_next_sg(tdc);
657 spin_unlock_irqrestore(&tdc->vc.lock, flags);
660 static int tegra_dma_stop_client(struct tegra_dma_channel *tdc)
670 csr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR);
673 tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, csr);
682 ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr +
683 tdc->chan_base_offset +
691 dev_err(tdc2dev(tdc), "Timeout waiting for DMA burst completion!\n");
692 tegra_dma_dump_chan_regs(tdc);
700 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
705 spin_lock_irqsave(&tdc->vc.lock, flags);
707 if (tdc->dma_desc) {
708 err = tdc->tdma->chip_data->terminate(tdc);
710 spin_unlock_irqrestore(&tdc->vc.lock, flags);
714 vchan_terminate_vdesc(&tdc->dma_desc->vd);
715 tegra_dma_disable(tdc);
716 tdc->dma_desc = NULL;
719 tegra_dma_sid_free(tdc);
720 vchan_get_all_descriptors(&tdc->vc, &head);
721 spin_unlock_irqrestore(&tdc->vc.lock, flags);
723 vchan_dma_desc_free_list(&tdc->vc, &head);
728 static int tegra_dma_get_residual(struct tegra_dma_channel *tdc)
730 struct tegra_dma_desc *dma_desc = tdc->dma_desc;
735 wcount = tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT);
742 status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
758 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
769 spin_lock_irqsave(&tdc->vc.lock, flags);
770 vd = vchan_find_desc(&tdc->vc, cookie);
775 } else if (tdc->dma_desc && tdc->dma_desc->vd.tx.cookie == cookie) {
776 residual = tegra_dma_get_residual(tdc);
779 dev_err(tdc2dev(tdc), "cookie %d is not found\n", cookie);
781 spin_unlock_irqrestore(&tdc->vc.lock, flags);
786 static inline int get_bus_width(struct tegra_dma_channel *tdc,
797 dev_err(tdc2dev(tdc), "given slave bus width is not supported\n");
802 static unsigned int get_burst_size(struct tegra_dma_channel *tdc,
825 static int get_transfer_param(struct tegra_dma_channel *tdc,
835 *apb_addr = tdc->dma_sconfig.dst_addr;
836 *mmio_seq = get_bus_width(tdc, tdc->dma_sconfig.dst_addr_width);
837 *burst_size = tdc->dma_sconfig.dst_maxburst;
838 *slave_bw = tdc->dma_sconfig.dst_addr_width;
842 *apb_addr = tdc->dma_sconfig.src_addr;
843 *mmio_seq = get_bus_width(tdc, tdc->dma_sconfig.src_addr_width);
844 *burst_size = tdc->dma_sconfig.src_maxburst;
845 *slave_bw = tdc->dma_sconfig.src_addr_width;
849 dev_err(tdc2dev(tdc), "DMA direction is not supported\n");
859 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
860 unsigned int max_dma_count = tdc->tdma->chip_data->max_dma_count;
866 dev_err(tdc2dev(tdc),
883 mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
919 return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags);
926 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
932 max_dma_count = tdc->tdma->chip_data->max_dma_count;
934 dev_err(tdc2dev(tdc),
951 mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
989 return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags);
997 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
998 unsigned int max_dma_count = tdc->tdma->chip_data->max_dma_count;
1008 if (!tdc->config_init) {
1009 dev_err(tdc2dev(tdc), "DMA channel is not configured\n");
1013 dev_err(tdc2dev(tdc), "Invalid segment length %d\n", sg_len);
1017 ret = tegra_dma_sid_reserve(tdc, direction);
1021 ret = get_transfer_param(tdc, direction, &apb_ptr, &mmio_seq, &csr,
1029 csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_REQ_SEL_MASK, tdc->slave_id);
1039 mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
1076 dev_err(tdc2dev(tdc),
1082 mmio_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
1109 return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags);
1120 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1127 dev_err(tdc2dev(tdc), "Invalid buffer/period len\n");
1131 if (!tdc->config_init) {
1132 dev_err(tdc2dev(tdc), "DMA slave is not configured\n");
1136 ret = tegra_dma_sid_reserve(tdc, direction);
1145 dev_err(tdc2dev(tdc), "buf_len is not multiple of period_len\n");
1150 max_dma_count = tdc->tdma->chip_data->max_dma_count;
1152 dev_err(tdc2dev(tdc), "Req len/mem address is not correct\n");
1156 ret = get_transfer_param(tdc, direction, &apb_ptr, &mmio_seq, &csr,
1164 csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_REQ_SEL_MASK, tdc->slave_id);
1176 mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
1206 mmio_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
1233 return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags);
1238 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1241 ret = request_irq(tdc->irq, tegra_dma_isr, 0, tdc->name, tdc);
1243 dev_err(tdc2dev(tdc), "request_irq failed for %s\n", tdc->name);
1247 dma_cookie_init(&tdc->vc.chan);
1248 tdc->config_init = false;
1254 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1256 synchronize_irq(tdc->irq);
1257 vchan_synchronize(&tdc->vc);
1262 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1264 dev_dbg(tdc2dev(tdc), "Freeing channel %d\n", tdc->id);
1267 synchronize_irq(tdc->irq);
1269 tasklet_kill(&tdc->vc.task);
1270 tdc->config_init = false;
1271 tdc->slave_id = -1;
1272 tdc->sid_dir = DMA_TRANS_NONE;
1273 free_irq(tdc->irq, tdc);
1275 vchan_free_chan_resources(&tdc->vc);
1282 struct tegra_dma_channel *tdc;
1289 tdc = to_tegra_dma_chan(chan);
1290 tdc->slave_id = dma_spec->args[0];
1334 static int tegra_dma_program_sid(struct tegra_dma_channel *tdc, int stream_id)
1336 unsigned int reg_val = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
1344 tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, reg_val);
1399 struct tegra_dma_channel *tdc = &tdma->channels[i];
1405 tdc->irq = platform_get_irq(pdev, i);
1406 if (tdc->irq < 0)
1407 return tdc->irq;
1409 tdc->chan_base_offset = TEGRA_GPCDMA_CHANNEL_BASE_ADDR_OFFSET +
1411 snprintf(tdc->name, sizeof(tdc->name), "gpcdma.%d", i);
1412 tdc->tdma = tdma;
1413 tdc->id = i;
1414 tdc->slave_id = -1;
1416 vchan_init(&tdc->vc, &tdma->dma_dev);
1417 tdc->vc.desc_free = tegra_dma_desc_free;
1420 tegra_dma_program_sid(tdc, stream_id);
1421 tdc->stream_id = stream_id;
1492 struct tegra_dma_channel *tdc = &tdma->channels[i];
1497 if (tdc->dma_desc) {
1514 struct tegra_dma_channel *tdc = &tdma->channels[i];
1519 tegra_dma_program_sid(tdc, tdc->stream_id);