Lines Matching refs:dmadev
289 static u32 stm32_mdma_read(struct stm32_mdma_device *dmadev, u32 reg)
291 return readl_relaxed(dmadev->base + reg);
294 static void stm32_mdma_write(struct stm32_mdma_device *dmadev, u32 reg, u32 val)
296 writel_relaxed(val, dmadev->base + reg);
299 static void stm32_mdma_set_bits(struct stm32_mdma_device *dmadev, u32 reg,
302 void __iomem *addr = dmadev->base + reg;
307 static void stm32_mdma_clr_bits(struct stm32_mdma_device *dmadev, u32 reg,
310 void __iomem *addr = dmadev->base + reg;
407 struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
415 stm32_mdma_clr_bits(dmadev, reg, STM32_MDMA_CCR_IRQ_MASK);
417 ccr = stm32_mdma_read(dmadev, reg);
419 stm32_mdma_clr_bits(dmadev, reg, STM32_MDMA_CCR_EN);
423 dmadev->base + STM32_MDMA_CISR(id), cisr,
436 struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
446 status = stm32_mdma_read(dmadev, STM32_MDMA_CISR(chan->id));
450 stm32_mdma_set_bits(dmadev, STM32_MDMA_CIFCR(chan->id), status);
456 static void stm32_mdma_set_bus(struct stm32_mdma_device *dmadev, u32 *ctbr,
465 for (i = 0; i < dmadev->nr_ahb_addr_masks; i++) {
466 if (mask == dmadev->ahb_addr_masks[i]) {
479 struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
492 ccr = stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id)) & ~STM32_MDMA_CCR_EN;
493 ctcr = stm32_mdma_read(dmadev, STM32_MDMA_CTCR(chan->id));
494 ctbr = stm32_mdma_read(dmadev, STM32_MDMA_CTBR(chan->id));
593 stm32_mdma_set_bus(dmadev, &ctbr, STM32_MDMA_CTBR_DBUS,
600 stm32_mdma_write(dmadev, STM32_MDMA_CDAR(chan->id), dst_addr);
651 stm32_mdma_set_bus(dmadev, &ctbr, STM32_MDMA_CTBR_SBUS,
658 stm32_mdma_write(dmadev, STM32_MDMA_CSAR(chan->id), src_addr);
730 struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
755 stm32_mdma_set_bus(dmadev, &ctbr, STM32_MDMA_CTBR_SBUS,
765 stm32_mdma_set_bus(dmadev, &ctbr, STM32_MDMA_CTBR_DBUS,
848 struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
888 stm32_mdma_set_bus(dmadev, &ctbr, STM32_MDMA_CTBR_SBUS,
894 stm32_mdma_set_bus(dmadev, &ctbr, STM32_MDMA_CTBR_DBUS,
942 struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
968 ccr = stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id)) & ~STM32_MDMA_CCR_EN;
969 ctcr = stm32_mdma_read(dmadev, STM32_MDMA_CTCR(chan->id));
970 ctbr = stm32_mdma_read(dmadev, STM32_MDMA_CTBR(chan->id));
971 cbndtr = stm32_mdma_read(dmadev, STM32_MDMA_CBNDTR(chan->id));
994 stm32_mdma_set_bus(dmadev, &ctbr, STM32_MDMA_CTBR_SBUS, src);
995 stm32_mdma_set_bus(dmadev, &ctbr, STM32_MDMA_CTBR_DBUS, dest);
1118 struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
1121 stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id)));
1123 stm32_mdma_read(dmadev, STM32_MDMA_CTCR(chan->id)));
1125 stm32_mdma_read(dmadev, STM32_MDMA_CBNDTR(chan->id)));
1127 stm32_mdma_read(dmadev, STM32_MDMA_CSAR(chan->id)));
1129 stm32_mdma_read(dmadev, STM32_MDMA_CDAR(chan->id)));
1131 stm32_mdma_read(dmadev, STM32_MDMA_CBRUR(chan->id)));
1133 stm32_mdma_read(dmadev, STM32_MDMA_CLAR(chan->id)));
1135 stm32_mdma_read(dmadev, STM32_MDMA_CTBR(chan->id)));
1137 stm32_mdma_read(dmadev, STM32_MDMA_CMAR(chan->id)));
1139 stm32_mdma_read(dmadev, STM32_MDMA_CMDR(chan->id)));
1144 struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
1162 stm32_mdma_write(dmadev, STM32_MDMA_CCR(id), chan->desc->ccr);
1163 stm32_mdma_write(dmadev, STM32_MDMA_CTCR(id), hwdesc->ctcr);
1164 stm32_mdma_write(dmadev, STM32_MDMA_CBNDTR(id), hwdesc->cbndtr);
1165 stm32_mdma_write(dmadev, STM32_MDMA_CSAR(id), hwdesc->csar);
1166 stm32_mdma_write(dmadev, STM32_MDMA_CDAR(id), hwdesc->cdar);
1167 stm32_mdma_write(dmadev, STM32_MDMA_CBRUR(id), hwdesc->cbrur);
1168 stm32_mdma_write(dmadev, STM32_MDMA_CLAR(id), hwdesc->clar);
1169 stm32_mdma_write(dmadev, STM32_MDMA_CTBR(id), hwdesc->ctbr);
1170 stm32_mdma_write(dmadev, STM32_MDMA_CMAR(id), hwdesc->cmar);
1171 stm32_mdma_write(dmadev, STM32_MDMA_CMDR(id), hwdesc->cmdr);
1174 status = stm32_mdma_read(dmadev, STM32_MDMA_CISR(id));
1176 stm32_mdma_set_bits(dmadev, STM32_MDMA_CIFCR(id), status);
1181 stm32_mdma_set_bits(dmadev, STM32_MDMA_CCR(id), STM32_MDMA_CCR_EN);
1186 stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CCR_SWRQ);
1232 struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
1238 if (!chan->desc || (stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id)) & STM32_MDMA_CCR_EN))
1246 stm32_mdma_write(dmadev, STM32_MDMA_CCR(chan->id), chan->desc->ccr);
1249 status = stm32_mdma_read(dmadev, STM32_MDMA_CISR(chan->id));
1251 stm32_mdma_set_bits(dmadev, STM32_MDMA_CIFCR(chan->id), status);
1257 stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CCR_EN);
1261 stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CCR_SWRQ);
1324 struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
1329 cisr = stm32_mdma_read(dmadev, STM32_MDMA_CISR(chan->id));
1333 clar = stm32_mdma_read(dmadev, STM32_MDMA_CLAR(chan->id));
1343 cbndtr = stm32_mdma_read(dmadev, STM32_MDMA_CBNDTR(chan->id));
1402 struct stm32_mdma_device *dmadev = devid;
1407 status = readl_relaxed(dmadev->base + STM32_MDMA_GISR0);
1409 dev_dbg(mdma2dev(dmadev), "spurious it\n");
1413 chan = &dmadev->chan[id];
1417 status = stm32_mdma_read(dmadev, STM32_MDMA_CISR(id));
1420 ccr = stm32_mdma_read(dmadev, STM32_MDMA_CCR(id));
1438 readl_relaxed(dmadev->base + STM32_MDMA_CESR(id)));
1439 stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CIFCR_CTEIF);
1444 stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CIFCR_CCTCIF);
1450 stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CIFCR_CBRTIF);
1455 stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CIFCR_CBTIF);
1466 stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CIFCR_CLTCIF);
1471 stm32_mdma_set_bits(dmadev, reg, status);
1485 struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
1498 ret = pm_runtime_resume_and_get(dmadev->ddev.dev);
1504 pm_runtime_put(dmadev->ddev.dev);
1512 struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
1524 pm_runtime_put(dmadev->ddev.dev);
1533 struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
1536 if (dmadev->chan_reserved & BIT(chan->id))
1545 struct stm32_mdma_device *dmadev = ofdma->of_dma_data;
1546 dma_cap_mask_t mask = dmadev->ddev.cap_mask;
1552 dev_err(mdma2dev(dmadev), "Bad number of args\n");
1563 if (config.request >= dmadev->nr_requests) {
1564 dev_err(mdma2dev(dmadev), "Bad request line\n");
1569 dev_err(mdma2dev(dmadev), "Priority level not supported\n");
1575 dev_err(mdma2dev(dmadev), "No more channels available\n");
1594 struct stm32_mdma_device *dmadev;
1625 dmadev = devm_kzalloc(&pdev->dev,
1626 struct_size(dmadev, ahb_addr_masks, count),
1628 if (!dmadev)
1631 dmadev->nr_channels = nr_channels;
1632 dmadev->nr_requests = nr_requests;
1634 dmadev->ahb_addr_masks,
1636 dmadev->nr_ahb_addr_masks = count;
1638 dmadev->base = devm_platform_ioremap_resource(pdev, 0);
1639 if (IS_ERR(dmadev->base))
1640 return PTR_ERR(dmadev->base);
1642 dmadev->clk = devm_clk_get(&pdev->dev, NULL);
1643 if (IS_ERR(dmadev->clk))
1644 return dev_err_probe(&pdev->dev, PTR_ERR(dmadev->clk),
1647 ret = clk_prepare_enable(dmadev->clk);
1664 dd = &dmadev->ddev;
1698 for (i = 0; i < dmadev->nr_channels; i++) {
1699 chan = &dmadev->chan[i];
1702 if (stm32_mdma_read(dmadev, STM32_MDMA_CCR(i)) & STM32_MDMA_CCR_SM)
1703 dmadev->chan_reserved |= BIT(i);
1709 dmadev->irq = platform_get_irq(pdev, 0);
1710 if (dmadev->irq < 0) {
1711 ret = dmadev->irq;
1715 ret = devm_request_irq(&pdev->dev, dmadev->irq, stm32_mdma_irq_handler,
1716 0, dev_name(&pdev->dev), dmadev);
1726 ret = of_dma_controller_register(of_node, stm32_mdma_of_xlate, dmadev);
1733 platform_set_drvdata(pdev, dmadev);
1744 clk_disable_unprepare(dmadev->clk);
1752 struct stm32_mdma_device *dmadev = dev_get_drvdata(dev);
1754 clk_disable_unprepare(dmadev->clk);
1761 struct stm32_mdma_device *dmadev = dev_get_drvdata(dev);
1764 ret = clk_prepare_enable(dmadev->clk);
1777 struct stm32_mdma_device *dmadev = dev_get_drvdata(dev);
1785 for (id = 0; id < dmadev->nr_channels; id++) {
1786 ccr = stm32_mdma_read(dmadev, STM32_MDMA_CCR(id));