Lines Matching refs:dmadev
257 static u32 stm32_dma_read(struct stm32_dma_device *dmadev, u32 reg)
259 return readl_relaxed(dmadev->base + reg);
262 static void stm32_dma_write(struct stm32_dma_device *dmadev, u32 reg, u32 val)
264 writel_relaxed(val, dmadev->base + reg);
419 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
427 dma_isr = stm32_dma_read(dmadev, STM32_DMA_ISR(chan->id));
435 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
445 stm32_dma_write(dmadev, STM32_DMA_IFCR(chan->id), dma_ifcr);
450 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
455 dma_scr = stm32_dma_read(dmadev, reg);
459 stm32_dma_write(dmadev, reg, dma_scr);
461 return readl_relaxed_poll_timeout_atomic(dmadev->base + reg,
471 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
476 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
478 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);
479 dma_sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id));
481 stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), dma_sfcr);
532 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
533 u32 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
534 u32 ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id));
535 u32 spar = stm32_dma_read(dmadev, STM32_DMA_SPAR(chan->id));
536 u32 sm0ar = stm32_dma_read(dmadev, STM32_DMA_SM0AR(chan->id));
537 u32 sm1ar = stm32_dma_read(dmadev, STM32_DMA_SM1AR(chan->id));
538 u32 sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id));
559 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
592 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr);
593 stm32_dma_write(dmadev, STM32_DMA_SPAR(chan->id), reg->dma_spar);
594 stm32_dma_write(dmadev, STM32_DMA_SM0AR(chan->id), reg->dma_sm0ar);
595 stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), reg->dma_sfcr);
596 stm32_dma_write(dmadev, STM32_DMA_SM1AR(chan->id), reg->dma_sm1ar);
597 stm32_dma_write(dmadev, STM32_DMA_SNDTR(chan->id), reg->dma_sndtr);
615 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr);
622 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
627 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
633 stm32_dma_write(dmadev, STM32_DMA_SM0AR(id), dma_sm0ar);
635 stm32_dma_read(dmadev, STM32_DMA_SM0AR(id)));
638 stm32_dma_write(dmadev, STM32_DMA_SM1AR(id), dma_sm1ar);
640 stm32_dma_read(dmadev, STM32_DMA_SM1AR(id)));
646 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
653 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
673 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);
676 chan->chan_reg.dma_sndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id));
685 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
690 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
703 stm32_dma_write(dmadev, STM32_DMA_SNDTR(chan->id), sg_req->chan_reg.dma_sndtr);
706 stm32_dma_write(dmadev, STM32_DMA_SPAR(id), sg_req->chan_reg.dma_spar);
709 stm32_dma_write(dmadev, STM32_DMA_SM0AR(id), sg_req->chan_reg.dma_sm0ar);
710 stm32_dma_write(dmadev, STM32_DMA_SM1AR(id), sg_req->chan_reg.dma_sm1ar);
723 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);
730 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);
764 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
770 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
771 sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id));
854 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
863 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
887 stm32_dma_write(dmadev, STM32_DMA_SPAR(id), spar + offset);
889 stm32_dma_write(dmadev, STM32_DMA_SPAR(id), spar);
900 stm32_dma_write(dmadev, STM32_DMA_SM1AR(id), sm1ar + offset);
902 stm32_dma_write(dmadev, STM32_DMA_SM0AR(id), sm0ar + offset);
905 stm32_dma_write(dmadev, STM32_DMA_SNDTR(id), chan_reg.dma_sndtr);
922 stm32_dma_write(dmadev, STM32_DMA_SCR(id), chan_reg.dma_scr);
1302 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
1304 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
1306 ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id));
1325 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
1330 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
1341 dma_smar = stm32_dma_read(dmadev, STM32_DMA_SM0AR(id));
1350 dma_smar = stm32_dma_read(dmadev, STM32_DMA_SM1AR(id));
1463 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
1468 ret = pm_runtime_resume_and_get(dmadev->ddev.dev);
1474 pm_runtime_put(dmadev->ddev.dev);
1482 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
1494 pm_runtime_put(dmadev->ddev.dev);
1528 struct stm32_dma_device *dmadev = ofdma->of_dma_data;
1529 struct device *dev = dmadev->ddev.dev;
1550 chan = &dmadev->chan[cfg.channel_id];
1572 struct stm32_dma_device *dmadev;
1585 dmadev = devm_kzalloc(&pdev->dev, sizeof(*dmadev), GFP_KERNEL);
1586 if (!dmadev)
1589 dd = &dmadev->ddev;
1591 dmadev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1592 if (IS_ERR(dmadev->base))
1593 return PTR_ERR(dmadev->base);
1595 dmadev->clk = devm_clk_get(&pdev->dev, NULL);
1596 if (IS_ERR(dmadev->clk))
1597 return dev_err_probe(&pdev->dev, PTR_ERR(dmadev->clk), "Can't get clock\n");
1599 ret = clk_prepare_enable(dmadev->clk);
1605 dmadev->mem2mem = of_property_read_bool(pdev->dev.of_node,
1650 if (dmadev->mem2mem) {
1657 chan = &dmadev->chan[i];
1674 chan = &dmadev->chan[i];
1692 stm32_dma_of_xlate, dmadev);
1699 platform_set_drvdata(pdev, dmadev);
1713 clk_disable_unprepare(dmadev->clk);
1721 struct stm32_dma_device *dmadev = dev_get_drvdata(dev);
1723 clk_disable_unprepare(dmadev->clk);
1730 struct stm32_dma_device *dmadev = dev_get_drvdata(dev);
1733 ret = clk_prepare_enable(dmadev->clk);
1746 struct stm32_dma_device *dmadev = dev_get_drvdata(dev);
1754 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));