Lines Matching defs:stm32_dma_write
262 static void stm32_dma_write(struct stm32_dma_device *dmadev, u32 reg, u32 val)
445 stm32_dma_write(dmadev, STM32_DMA_IFCR(chan->id), dma_ifcr);
459 stm32_dma_write(dmadev, reg, dma_scr);
478 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);
481 stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), dma_sfcr);
592 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr);
593 stm32_dma_write(dmadev, STM32_DMA_SPAR(chan->id), reg->dma_spar);
594 stm32_dma_write(dmadev, STM32_DMA_SM0AR(chan->id), reg->dma_sm0ar);
595 stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), reg->dma_sfcr);
596 stm32_dma_write(dmadev, STM32_DMA_SM1AR(chan->id), reg->dma_sm1ar);
597 stm32_dma_write(dmadev, STM32_DMA_SNDTR(chan->id), reg->dma_sndtr);
615 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr);
633 stm32_dma_write(dmadev, STM32_DMA_SM0AR(id), dma_sm0ar);
638 stm32_dma_write(dmadev, STM32_DMA_SM1AR(id), dma_sm1ar);
673 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);
703 stm32_dma_write(dmadev, STM32_DMA_SNDTR(chan->id), sg_req->chan_reg.dma_sndtr);
706 stm32_dma_write(dmadev, STM32_DMA_SPAR(id), sg_req->chan_reg.dma_spar);
709 stm32_dma_write(dmadev, STM32_DMA_SM0AR(id), sg_req->chan_reg.dma_sm0ar);
710 stm32_dma_write(dmadev, STM32_DMA_SM1AR(id), sg_req->chan_reg.dma_sm1ar);
723 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);
730 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);
887 stm32_dma_write(dmadev, STM32_DMA_SPAR(id), spar + offset);
889 stm32_dma_write(dmadev, STM32_DMA_SPAR(id), spar);
900 stm32_dma_write(dmadev, STM32_DMA_SM1AR(id), sm1ar + offset);
902 stm32_dma_write(dmadev, STM32_DMA_SM0AR(id), sm0ar + offset);
905 stm32_dma_write(dmadev, STM32_DMA_SNDTR(id), chan_reg.dma_sndtr);
922 stm32_dma_write(dmadev, STM32_DMA_SCR(id), chan_reg.dma_scr);