Lines Matching defs:dma_scr
177 u32 dma_scr;
387 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_DMEIE;
391 chan->chan_reg.dma_scr |= STM32_DMA_SCR_DMEIE;
451 u32 dma_scr, id, reg;
455 dma_scr = stm32_dma_read(dmadev, reg);
457 if (dma_scr & STM32_DMA_SCR_EN) {
458 dma_scr &= ~STM32_DMA_SCR_EN;
459 stm32_dma_write(dmadev, reg, dma_scr);
462 dma_scr, !(dma_scr & STM32_DMA_SCR_EN),
472 u32 dma_scr, dma_sfcr, status;
476 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
477 dma_scr &= ~STM32_DMA_SCR_IRQ_MASK;
478 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);
589 reg->dma_scr &= ~STM32_DMA_SCR_TCIE;
591 reg->dma_scr &= ~STM32_DMA_SCR_EN;
592 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr);
614 reg->dma_scr |= STM32_DMA_SCR_EN;
615 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr);
624 u32 dma_scr, dma_sm0ar, dma_sm1ar, id;
627 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
631 if (dma_scr & STM32_DMA_SCR_CT) {
647 u32 dma_scr;
653 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
661 dma_scr |= STM32_DMA_SCR_CIRC;
663 dma_scr |= STM32_DMA_SCR_DBM;
665 chan->chan_reg.dma_scr = dma_scr;
672 dma_scr &= ~(STM32_DMA_SCR_DBM | STM32_DMA_SCR_CIRC);
673 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);
687 u32 dma_scr, status, id;
690 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
713 if (chan->chan_reg.dma_scr & STM32_DMA_SCR_DBM) {
714 dma_scr |= STM32_DMA_SCR_DBM;
716 if (chan->chan_reg.dma_scr & STM32_DMA_SCR_CT)
717 dma_scr &= ~STM32_DMA_SCR_CT;
719 dma_scr |= STM32_DMA_SCR_CT;
720 } else if (chan->chan_reg.dma_scr & STM32_DMA_SCR_CIRC) {
721 dma_scr |= STM32_DMA_SCR_CIRC;
723 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);
729 dma_scr |= STM32_DMA_SCR_EN;
730 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);
877 offset <<= FIELD_GET(STM32_DMA_SCR_PSIZE_MASK, chan_reg.dma_scr);
886 if (chan_reg.dma_scr & STM32_DMA_SCR_PINC)
891 if (!(chan_reg.dma_scr & STM32_DMA_SCR_MINC))
899 if ((chan_reg.dma_scr & STM32_DMA_SCR_DBM) && (chan_reg.dma_scr & STM32_DMA_SCR_CT))
911 if (chan_reg.dma_scr & (STM32_DMA_SCR_CIRC | STM32_DMA_SCR_DBM))
912 chan_reg.dma_scr &= ~(STM32_DMA_SCR_CIRC | STM32_DMA_SCR_DBM);
914 if (chan_reg.dma_scr & STM32_DMA_SCR_DBM)
921 chan_reg.dma_scr |= STM32_DMA_SCR_EN;
922 stm32_dma_write(dmadev, STM32_DMA_SCR(id), chan_reg.dma_scr);
940 u32 dma_scr, fifoth;
989 dma_scr = FIELD_PREP(STM32_DMA_SCR_DIR_MASK, STM32_DMA_MEM_TO_DEV) |
1046 dma_scr = FIELD_PREP(STM32_DMA_SCR_DIR_MASK, STM32_DMA_DEV_TO_MEM) |
1070 chan->chan_reg.dma_scr &= ~(STM32_DMA_SCR_DIR_MASK |
1073 chan->chan_reg.dma_scr |= dma_scr;
1111 chan->chan_reg.dma_scr |= STM32_DMA_SCR_PFCTRL;
1113 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL;
1117 chan->chan_reg.dma_scr |= STM32_DMA_SCR_DBM;
1118 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_CT;
1137 desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr;
1207 chan->chan_reg.dma_scr |= STM32_DMA_SCR_CIRC;
1209 chan->chan_reg.dma_scr |= STM32_DMA_SCR_DBM;
1210 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_CT;
1214 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL;
1226 desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr;
1277 desc->sg_req[i].chan_reg.dma_scr =
1301 u32 dma_scr, width, ndtr;
1304 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
1305 width = FIELD_GET(STM32_DMA_SCR_PSIZE_MASK, dma_scr);
1327 u32 dma_scr, dma_smar, id, period_len;
1330 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
1333 if (!(dma_scr & STM32_DMA_SCR_DBM))
1340 if (dma_scr & STM32_DMA_SCR_CT) {
1511 chan->chan_reg.dma_scr = cfg->stream_config & STM32_DMA_SCR_CFG_MASK;
1512 chan->chan_reg.dma_scr |= FIELD_PREP(STM32_DMA_SCR_REQ_MASK, cfg->request_line);
1515 chan->chan_reg.dma_scr |= STM32_DMA_SCR_TEIE | STM32_DMA_SCR_TCIE;
1521 chan->chan_reg.dma_scr |= STM32_DMA_SCR_TRBUFF;