Lines Matching defs:chan_reg
187 struct stm32_dma_chan_reg chan_reg;
219 struct stm32_dma_chan_reg chan_reg;
386 chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_MASK;
387 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_DMEIE;
391 chan->chan_reg.dma_scr |= STM32_DMA_SCR_DMEIE;
394 chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK;
585 reg = &sg_req->chan_reg;
632 dma_sm0ar = sg_req->chan_reg.dma_sm0ar;
637 dma_sm1ar = sg_req->chan_reg.dma_sm1ar;
665 chan->chan_reg.dma_scr = dma_scr;
676 chan->chan_reg.dma_sndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id));
703 stm32_dma_write(dmadev, STM32_DMA_SNDTR(chan->id), sg_req->chan_reg.dma_sndtr);
706 stm32_dma_write(dmadev, STM32_DMA_SPAR(id), sg_req->chan_reg.dma_spar);
709 stm32_dma_write(dmadev, STM32_DMA_SM0AR(id), sg_req->chan_reg.dma_sm0ar);
710 stm32_dma_write(dmadev, STM32_DMA_SM1AR(id), sg_req->chan_reg.dma_sm1ar);
713 if (chan->chan_reg.dma_scr & STM32_DMA_SCR_DBM) {
716 if (chan->chan_reg.dma_scr & STM32_DMA_SCR_CT)
720 } else if (chan->chan_reg.dma_scr & STM32_DMA_SCR_CIRC) {
855 struct stm32_dma_chan_reg chan_reg = chan->chan_reg;
875 ndtr = sg_req->chan_reg.dma_sndtr;
876 offset = (ndtr - chan_reg.dma_sndtr);
877 offset <<= FIELD_GET(STM32_DMA_SCR_PSIZE_MASK, chan_reg.dma_scr);
878 spar = sg_req->chan_reg.dma_spar;
879 sm0ar = sg_req->chan_reg.dma_sm0ar;
880 sm1ar = sg_req->chan_reg.dma_sm1ar;
886 if (chan_reg.dma_scr & STM32_DMA_SCR_PINC)
891 if (!(chan_reg.dma_scr & STM32_DMA_SCR_MINC))
899 if ((chan_reg.dma_scr & STM32_DMA_SCR_DBM) && (chan_reg.dma_scr & STM32_DMA_SCR_CT))
905 stm32_dma_write(dmadev, STM32_DMA_SNDTR(id), chan_reg.dma_sndtr);
911 if (chan_reg.dma_scr & (STM32_DMA_SCR_CIRC | STM32_DMA_SCR_DBM))
912 chan_reg.dma_scr &= ~(STM32_DMA_SCR_CIRC | STM32_DMA_SCR_DBM);
914 if (chan_reg.dma_scr & STM32_DMA_SCR_DBM)
921 chan_reg.dma_scr |= STM32_DMA_SCR_EN;
922 stm32_dma_write(dmadev, STM32_DMA_SCR(id), chan_reg.dma_scr);
996 chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK;
998 chan->chan_reg.dma_sfcr |= FIELD_PREP(STM32_DMA_SFCR_FTH_MASK, fifoth);
1001 chan->chan_reg.dma_spar = chan->dma_sconfig.dst_addr;
1053 chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK;
1055 chan->chan_reg.dma_sfcr |= FIELD_PREP(STM32_DMA_SFCR_FTH_MASK, fifoth);
1058 chan->chan_reg.dma_spar = chan->dma_sconfig.src_addr;
1070 chan->chan_reg.dma_scr &= ~(STM32_DMA_SCR_DIR_MASK |
1073 chan->chan_reg.dma_scr |= dma_scr;
1111 chan->chan_reg.dma_scr |= STM32_DMA_SCR_PFCTRL;
1113 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL;
1117 chan->chan_reg.dma_scr |= STM32_DMA_SCR_DBM;
1118 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_CT;
1136 stm32_dma_clear_reg(&desc->sg_req[i].chan_reg);
1137 desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr;
1138 desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr;
1139 desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar;
1140 desc->sg_req[i].chan_reg.dma_sm0ar = sg_dma_address(sg);
1141 desc->sg_req[i].chan_reg.dma_sm1ar = sg_dma_address(sg);
1143 desc->sg_req[i].chan_reg.dma_sm1ar += sg_dma_len(sg);
1144 desc->sg_req[i].chan_reg.dma_sndtr = nb_data_items;
1207 chan->chan_reg.dma_scr |= STM32_DMA_SCR_CIRC;
1209 chan->chan_reg.dma_scr |= STM32_DMA_SCR_DBM;
1210 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_CT;
1214 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL;
1225 stm32_dma_clear_reg(&desc->sg_req[i].chan_reg);
1226 desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr;
1227 desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr;
1228 desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar;
1229 desc->sg_req[i].chan_reg.dma_sm0ar = buf_addr;
1230 desc->sg_req[i].chan_reg.dma_sm1ar = buf_addr;
1232 desc->sg_req[i].chan_reg.dma_sm1ar += period_len;
1233 desc->sg_req[i].chan_reg.dma_sndtr = nb_data_items;
1276 stm32_dma_clear_reg(&desc->sg_req[i].chan_reg);
1277 desc->sg_req[i].chan_reg.dma_scr =
1285 desc->sg_req[i].chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK;
1286 desc->sg_req[i].chan_reg.dma_sfcr |= FIELD_PREP(STM32_DMA_SFCR_FTH_MASK, threshold);
1287 desc->sg_req[i].chan_reg.dma_spar = src + offset;
1288 desc->sg_req[i].chan_reg.dma_sm0ar = dest + offset;
1289 desc->sg_req[i].chan_reg.dma_sndtr = xfer_count;
1346 return (dma_smar >= sg_req->chan_reg.dma_sm0ar &&
1347 dma_smar < sg_req->chan_reg.dma_sm0ar + period_len);
1355 return (dma_smar >= sg_req->chan_reg.dma_sm1ar &&
1356 dma_smar < sg_req->chan_reg.dma_sm1ar + period_len);
1497 stm32_dma_clear_reg(&chan->chan_reg);
1509 stm32_dma_clear_reg(&chan->chan_reg);
1511 chan->chan_reg.dma_scr = cfg->stream_config & STM32_DMA_SCR_CFG_MASK;
1512 chan->chan_reg.dma_scr |= FIELD_PREP(STM32_DMA_SCR_REQ_MASK, cfg->request_line);
1515 chan->chan_reg.dma_scr |= STM32_DMA_SCR_TEIE | STM32_DMA_SCR_TCIE;
1521 chan->chan_reg.dma_scr |= STM32_DMA_SCR_TRBUFF;