Lines Matching refs:virtbase
554 * @virtbase: The virtual base address of the DMA's register.
597 void __iomem *virtbase;
645 return chan->base->virtbase + D40_DREG_PCBASE +
1082 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1084 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1299 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1301 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1383 writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base);
1388 writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base);
1680 regs[i] = readl(base->virtbase + il[i].src);
1708 writel(BIT(idx), base->virtbase + il[row].clr);
2086 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
2088 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
2345 writel(bit, d40c->base->virtbase + prioreg + group * 4);
2346 writel(bit, d40c->base->virtbase + rtreg + group * 4);
2986 addr = base->virtbase + D40_DREG_PCBASE + i * D40_DREG_PCDELTA;
2996 dma40_backup(base->virtbase, base->reg_val_backup,
3002 dma40_backup(base->virtbase, base->reg_val_backup_v4,
3017 base->virtbase + D40_DREG_GCC);
3029 base->virtbase + D40_DREG_GCC);
3051 val[0] = readl(base->virtbase + D40_DREG_PRSME);
3052 val[1] = readl(base->virtbase + D40_DREG_PRSMO);
3102 val[0] = readl(base->virtbase + D40_DREG_PRTYP);
3121 writel(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC);
3141 void __iomem *virtbase;
3157 virtbase = devm_platform_ioremap_resource_byname(pdev, "base");
3158 if (IS_ERR(virtbase))
3159 return PTR_ERR(virtbase);
3163 pid |= (readl(virtbase + SZ_4K - 0x20 + 4 * i)
3166 cid |= (readl(virtbase + SZ_4K - 0x10 + 4 * i)
3198 num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
3225 base->virtbase = virtbase;
3327 base->virtbase + dma_init_reg[i].reg);
3352 writel(prmseo[1], base->virtbase + D40_DREG_PRMSE);
3353 writel(prmseo[0], base->virtbase + D40_DREG_PRMSO);
3354 writel(activeo[1], base->virtbase + D40_DREG_ACTIVE);
3355 writel(activeo[0], base->virtbase + D40_DREG_ACTIVO);
3358 writel(pcmis, base->virtbase + base->gen_dmac.interrupt_en);
3361 writel(pcicr, base->virtbase + base->gen_dmac.interrupt_clear);
3444 base->virtbase + D40_DREG_LCLA);
3549 val = readl(base->virtbase + D40_DREG_LCPA);
3555 writel(base->phy_lcpa, base->virtbase + D40_DREG_LCPA);
3580 writel(res->start, base->virtbase + D40_DREG_LCLA);
3624 writel_relaxed(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC);