Lines Matching refs:ret
731 int ret = -EINVAL;
745 ret = i;
752 return ret;
760 int ret = -EINVAL;
774 ret = 0;
782 return ret;
1051 int ret;
1054 ret = d40_size_2_dmalen(sg_dma_len(sg),
1056 if (ret < 0)
1057 return ret;
1058 len += ret;
1069 int ret = 0;
1074 ret = __d40_execute_command_phy(d40c, D40_DMA_SUSPEND_REQ);
1075 if (ret)
1076 return ret;
1124 ret = -EBUSY;
1130 return ret;
1294 int ret = 0;
1320 ret = __d40_execute_command_phy(d40c, command);
1327 ret = __d40_execute_command_phy(d40c, command);
1336 return ret;
2142 int ret;
2144 ret = d40_log_sg_to_lli(sg_src, sg_len,
2151 ret = d40_log_sg_to_lli(sg_dst, sg_len,
2158 return ret < 0 ? ret : 0;
2171 int ret;
2176 ret = d40_phy_sg_to_lli(sg_src, sg_len, src_dev_addr,
2182 ret = d40_phy_sg_to_lli(sg_dst, sg_len, dst_dev_addr,
2191 return ret < 0 ? ret : 0;
2200 int ret;
2214 ret = d40_pool_lli_alloc(chan, desc, desc->lli_len);
2215 if (ret < 0) {
2242 int ret;
2268 ret = d40_prep_sg_log(chan, desc, sg_src, sg_dst,
2271 ret = d40_prep_sg_phy(chan, desc, sg_src, sg_dst,
2274 if (ret) {
2276 chan_is_logical(chan) ? "log" : "phy", ret);
2566 enum dma_status ret;
2573 ret = dma_cookie_status(chan, cookie, txstate);
2574 if (ret != DMA_COMPLETE && txstate)
2578 ret = DMA_PAUSED;
2580 return ret;
2608 int ret;
2618 ret = d40_channel_execute_command(d40c, D40_DMA_STOP);
2619 if (ret)
2688 int ret;
2773 ret = dma40_config_to_halfchannel(d40c, &cfg->src_info,
2775 if (ret)
2776 return ret;
2778 ret = dma40_config_to_halfchannel(d40c, &cfg->dst_info,
2780 if (ret)
2781 return ret;
2932 int ret;
2934 ret = pm_runtime_force_suspend(dev);
2935 if (ret)
2936 return ret;
2939 ret = regulator_disable(base->lcpa_regulator);
2940 return ret;
2946 int ret = 0;
2949 ret = regulator_enable(base->lcpa_regulator);
2950 if (ret)
2951 return ret;
3150 int ret;
3304 ret = devm_add_action_or_reset(dev, d40_drop_kmem_cache_action,
3306 if (ret)
3307 return ret;
3373 int ret;
3396 ret = -ENOMEM;
3426 ret = -ENOMEM;
3439 ret = -ENOMEM;
3445 ret = 0;
3448 return ret;
3512 int ret;
3515 ret = -ENOMEM;
3519 ret = d40_hw_detect_init(pdev, &base);
3520 if (ret)
3534 ret = -EINVAL;
3538 ret = of_address_to_resource(np_lcpa, 0, &res_lcpa);
3539 if (ret) {
3559 ret = -ENOMEM;
3568 ret = -ENOENT;
3576 ret = -ENOMEM;
3583 ret = d40_lcla_allocate(base);
3584 if (ret) {
3594 ret = base->irq;
3598 ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base);
3599 if (ret) {
3609 ret = PTR_ERR(base->lcpa_regulator);
3614 ret = regulator_enable(base->lcpa_regulator);
3615 if (ret) {
3633 ret = d40_dmaengine_init(base, num_reserved_chans);
3634 if (ret)
3637 ret = dma_set_max_seg_size(base->dev, STEDMA40_MAX_SEG_SIZE);
3638 if (ret) {
3645 ret = of_dma_controller_register(np, d40_xlate, NULL);
3646 if (ret) {
3675 return ret;