Lines Matching defs:gen_dmac
590 * @gen_dmac: the struct for generic registers values to represent u8500/8540
625 struct d40_gen_dmac gen_dmac;
1673 struct d40_interrupt_lookup *il = base->gen_dmac.il;
1674 u32 il_size = base->gen_dmac.il_size;
2325 struct d40_gen_dmac *dmac = &d40c->base->gen_dmac;
3001 if (base->gen_dmac.backup)
3003 base->gen_dmac.backup,
3004 base->gen_dmac.backup_size,
3232 base->gen_dmac.backup = d40_backup_regs_v4b;
3233 base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4B;
3234 base->gen_dmac.interrupt_en = D40_DREG_CPCMIS;
3235 base->gen_dmac.interrupt_clear = D40_DREG_CPCICR;
3236 base->gen_dmac.realtime_en = D40_DREG_CRSEG1;
3237 base->gen_dmac.realtime_clear = D40_DREG_CRCEG1;
3238 base->gen_dmac.high_prio_en = D40_DREG_CPSEG1;
3239 base->gen_dmac.high_prio_clear = D40_DREG_CPCEG1;
3240 base->gen_dmac.il = il_v4b;
3241 base->gen_dmac.il_size = ARRAY_SIZE(il_v4b);
3242 base->gen_dmac.init_reg = dma_init_reg_v4b;
3243 base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4b);
3246 base->gen_dmac.backup = d40_backup_regs_v4a;
3247 base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4A;
3249 base->gen_dmac.interrupt_en = D40_DREG_PCMIS;
3250 base->gen_dmac.interrupt_clear = D40_DREG_PCICR;
3251 base->gen_dmac.realtime_en = D40_DREG_RSEG1;
3252 base->gen_dmac.realtime_clear = D40_DREG_RCEG1;
3253 base->gen_dmac.high_prio_en = D40_DREG_PSEG1;
3254 base->gen_dmac.high_prio_clear = D40_DREG_PCEG1;
3255 base->gen_dmac.il = il_v4a;
3256 base->gen_dmac.il_size = ARRAY_SIZE(il_v4a);
3257 base->gen_dmac.init_reg = dma_init_reg_v4a;
3258 base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4a);
3292 base->regs_interrupt = devm_kmalloc_array(dev, base->gen_dmac.il_size,
3322 struct d40_reg_val *dma_init_reg = base->gen_dmac.init_reg;
3323 u32 reg_size = base->gen_dmac.init_reg_size;
3358 writel(pcmis, base->virtbase + base->gen_dmac.interrupt_en);
3361 writel(pcicr, base->virtbase + base->gen_dmac.interrupt_clear);
3364 base->gen_dmac.init_reg = NULL;
3365 base->gen_dmac.init_reg_size = 0;