Lines Matching defs:adev
121 struct adm_device *adev;
137 struct adm_device *adev;
354 struct adm_device *adev = achan->adev;
365 dev_err(adev->dev, "invalid dma direction\n");
380 dev_err(adev->dev, "invalid burst value: %d\n",
387 dev_err(adev->dev, "invalid crci value\n");
407 dev_err(adev->dev, "not enough memory for async_desc struct\n");
420 dev_err(adev->dev, "not enough memory for cpl struct\n");
424 async_desc->adev = adev;
441 async_desc->dma_addr = dma_map_single(adev->dev, async_desc->cpl,
444 if (dma_mapping_error(adev->dev, async_desc->dma_addr)) {
445 dev_err(adev->dev, "dma mapping error for cpl\n");
452 dma_sync_single_for_cpu(adev->dev, cple_addr, sizeof(*cple),
456 dma_sync_single_for_device(adev->dev, cple_addr, sizeof(*cple),
477 struct adm_device *adev = achan->adev;
486 adev->regs + ADM_CH_FLUSH_STATE0(achan->id, adev->ee));
517 struct adm_device *adev = achan->adev;
539 ADM_CH_CONF_SEC_DOMAIN(adev->ee),
540 adev->regs + ADM_CH_CONF(achan->id));
543 adev->regs + ADM_CH_RSLT_CONF(achan->id, adev->ee));
551 adev->regs + ADM_CRCI_CTL(async_desc->crci, adev->ee));
559 adev->regs + ADM_CH_CMD_PTR(achan->id, adev->ee));
571 struct adm_device *adev = data;
576 srcs = readl_relaxed(adev->regs +
577 ADM_SEC_DOMAIN_IRQ_STATUS(adev->ee));
580 struct adm_chan *achan = &adev->channels[i];
584 status = readl_relaxed(adev->regs +
585 ADM_CH_STATUS_SD(i, adev->ee));
591 result = readl_relaxed(adev->regs +
592 ADM_CH_RSLT(i, adev->ee));
691 dma_unmap_single(async_desc->adev->dev, async_desc->dma_addr,
697 static void adm_channel_init(struct adm_device *adev, struct adm_chan *achan,
701 achan->adev = adev;
703 vchan_init(&achan->vc, &adev->common);
748 struct adm_device *adev;
752 adev = devm_kzalloc(&pdev->dev, sizeof(*adev), GFP_KERNEL);
753 if (!adev)
756 adev->dev = &pdev->dev;
758 adev->regs = devm_platform_ioremap_resource(pdev, 0);
759 if (IS_ERR(adev->regs))
760 return PTR_ERR(adev->regs);
762 adev->irq = platform_get_irq(pdev, 0);
763 if (adev->irq < 0)
764 return adev->irq;
766 ret = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &adev->ee);
768 dev_err(adev->dev, "Execution environment unspecified\n");
772 adev->core_clk = devm_clk_get(adev->dev, "core");
773 if (IS_ERR(adev->core_clk))
774 return PTR_ERR(adev->core_clk);
776 adev->iface_clk = devm_clk_get(adev->dev, "iface");
777 if (IS_ERR(adev->iface_clk))
778 return PTR_ERR(adev->iface_clk);
780 adev->clk_reset = devm_reset_control_get_exclusive(&pdev->dev, "clk");
781 if (IS_ERR(adev->clk_reset)) {
782 dev_err(adev->dev, "failed to get ADM0 reset\n");
783 return PTR_ERR(adev->clk_reset);
786 adev->c0_reset = devm_reset_control_get_exclusive(&pdev->dev, "c0");
787 if (IS_ERR(adev->c0_reset)) {
788 dev_err(adev->dev, "failed to get ADM0 C0 reset\n");
789 return PTR_ERR(adev->c0_reset);
792 adev->c1_reset = devm_reset_control_get_exclusive(&pdev->dev, "c1");
793 if (IS_ERR(adev->c1_reset)) {
794 dev_err(adev->dev, "failed to get ADM0 C1 reset\n");
795 return PTR_ERR(adev->c1_reset);
798 adev->c2_reset = devm_reset_control_get_exclusive(&pdev->dev, "c2");
799 if (IS_ERR(adev->c2_reset)) {
800 dev_err(adev->dev, "failed to get ADM0 C2 reset\n");
801 return PTR_ERR(adev->c2_reset);
804 ret = clk_prepare_enable(adev->core_clk);
806 dev_err(adev->dev, "failed to prepare/enable core clock\n");
810 ret = clk_prepare_enable(adev->iface_clk);
812 dev_err(adev->dev, "failed to prepare/enable iface clock\n");
816 reset_control_assert(adev->clk_reset);
817 reset_control_assert(adev->c0_reset);
818 reset_control_assert(adev->c1_reset);
819 reset_control_assert(adev->c2_reset);
823 reset_control_deassert(adev->clk_reset);
824 reset_control_deassert(adev->c0_reset);
825 reset_control_deassert(adev->c1_reset);
826 reset_control_deassert(adev->c2_reset);
828 adev->channels = devm_kcalloc(adev->dev, ADM_MAX_CHANNELS,
829 sizeof(*adev->channels), GFP_KERNEL);
831 if (!adev->channels) {
837 INIT_LIST_HEAD(&adev->common.channels);
840 adm_channel_init(adev, &adev->channels[i], i);
844 writel(ADM_CRCI_CTL_RST, adev->regs +
845 ADM_CRCI_CTL(i, adev->ee));
849 ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(0));
851 ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(1));
853 ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(2));
855 adev->regs + ADM_GP_CTL);
857 ret = devm_request_irq(adev->dev, adev->irq, adm_dma_irq,
858 0, "adm_dma", adev);
862 platform_set_drvdata(pdev, adev);
864 adev->common.dev = adev->dev;
865 adev->common.dev->dma_parms = &adev->dma_parms;
868 dma_cap_zero(adev->common.cap_mask);
869 dma_cap_set(DMA_SLAVE, adev->common.cap_mask);
870 dma_cap_set(DMA_PRIVATE, adev->common.cap_mask);
873 adev->common.directions = BIT(DMA_DEV_TO_MEM | DMA_MEM_TO_DEV);
874 adev->common.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
875 adev->common.src_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES;
876 adev->common.dst_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES;
877 adev->common.device_free_chan_resources = adm_free_chan;
878 adev->common.device_prep_slave_sg = adm_prep_slave_sg;
879 adev->common.device_issue_pending = adm_issue_pending;
880 adev->common.device_tx_status = adm_tx_status;
881 adev->common.device_terminate_all = adm_terminate_all;
882 adev->common.device_config = adm_slave_config;
884 ret = dma_async_device_register(&adev->common);
886 dev_err(adev->dev, "failed to register dma async device\n");
891 &adev->common);
898 dma_async_device_unregister(&adev->common);
900 clk_disable_unprepare(adev->iface_clk);
902 clk_disable_unprepare(adev->core_clk);
909 struct adm_device *adev = platform_get_drvdata(pdev);
914 dma_async_device_unregister(&adev->common);
917 achan = &adev->channels[i];
920 writel(0, adev->regs + ADM_CH_RSLT_CONF(achan->id, adev->ee));
922 tasklet_kill(&adev->channels[i].vc.task);
923 adm_terminate_all(&adev->channels[i].vc.chan);
926 devm_free_irq(adev->dev, adev->irq, adev);
928 clk_disable_unprepare(adev->core_clk);
929 clk_disable_unprepare(adev->iface_clk);