Lines Matching defs:mgmtdev
67 int hidma_mgmt_setup(struct hidma_mgmt_dev *mgmtdev)
72 if (!is_power_of_2(mgmtdev->max_write_request) ||
73 (mgmtdev->max_write_request < 128) ||
74 (mgmtdev->max_write_request > 1024)) {
75 dev_err(&mgmtdev->pdev->dev, "invalid write request %d\n",
76 mgmtdev->max_write_request);
80 if (!is_power_of_2(mgmtdev->max_read_request) ||
81 (mgmtdev->max_read_request < 128) ||
82 (mgmtdev->max_read_request > 1024)) {
83 dev_err(&mgmtdev->pdev->dev, "invalid read request %d\n",
84 mgmtdev->max_read_request);
88 if (mgmtdev->max_wr_xactions > HIDMA_MAX_WR_XACTIONS_MASK) {
89 dev_err(&mgmtdev->pdev->dev,
95 if (mgmtdev->max_rd_xactions > HIDMA_MAX_RD_XACTIONS_MASK) {
96 dev_err(&mgmtdev->pdev->dev,
102 for (i = 0; i < mgmtdev->dma_channels; i++) {
103 if (mgmtdev->priority[i] > 1) {
104 dev_err(&mgmtdev->pdev->dev,
109 if (mgmtdev->weight[i] > HIDMA_MAX_CHANNEL_WEIGHT) {
110 dev_err(&mgmtdev->pdev->dev,
117 if (mgmtdev->weight[i] == 0)
118 mgmtdev->weight[i] = 1;
121 pm_runtime_get_sync(&mgmtdev->pdev->dev);
122 val = readl(mgmtdev->virtaddr + HIDMA_MAX_BUS_REQ_LEN_OFFSET);
124 val |= mgmtdev->max_write_request << HIDMA_MAX_BUS_WR_REQ_BIT_POS;
126 val |= mgmtdev->max_read_request;
127 writel(val, mgmtdev->virtaddr + HIDMA_MAX_BUS_REQ_LEN_OFFSET);
129 val = readl(mgmtdev->virtaddr + HIDMA_MAX_XACTIONS_OFFSET);
131 val |= mgmtdev->max_wr_xactions << HIDMA_MAX_WR_XACTIONS_BIT_POS;
133 val |= mgmtdev->max_rd_xactions;
134 writel(val, mgmtdev->virtaddr + HIDMA_MAX_XACTIONS_OFFSET);
136 mgmtdev->hw_version =
137 readl(mgmtdev->virtaddr + HIDMA_HW_VERSION_OFFSET);
138 mgmtdev->hw_version_major = (mgmtdev->hw_version >> 28) & 0xF;
139 mgmtdev->hw_version_minor = (mgmtdev->hw_version >> 16) & 0xF;
141 for (i = 0; i < mgmtdev->dma_channels; i++) {
142 u32 weight = mgmtdev->weight[i];
143 u32 priority = mgmtdev->priority[i];
145 val = readl(mgmtdev->virtaddr + HIDMA_QOS_N_OFFSET + (4 * i));
150 writel(val, mgmtdev->virtaddr + HIDMA_QOS_N_OFFSET + (4 * i));
153 val = readl(mgmtdev->virtaddr + HIDMA_CHRESET_TIMEOUT_OFFSET);
155 val |= mgmtdev->chreset_timeout_cycles & HIDMA_CHRESET_TIMEOUT_MASK;
156 writel(val, mgmtdev->virtaddr + HIDMA_CHRESET_TIMEOUT_OFFSET);
158 pm_runtime_mark_last_busy(&mgmtdev->pdev->dev);
159 pm_runtime_put_autosuspend(&mgmtdev->pdev->dev);
166 struct hidma_mgmt_dev *mgmtdev;
191 mgmtdev = devm_kzalloc(&pdev->dev, sizeof(*mgmtdev), GFP_KERNEL);
192 if (!mgmtdev) {
197 mgmtdev->pdev = pdev;
198 mgmtdev->addrsize = resource_size(res);
199 mgmtdev->virtaddr = virtaddr;
202 &mgmtdev->dma_channels);
210 &mgmtdev->chreset_timeout_cycles);
217 &mgmtdev->max_write_request);
224 (max_write_request != mgmtdev->max_write_request)) {
227 mgmtdev->max_write_request = max_write_request;
229 max_write_request = mgmtdev->max_write_request;
232 &mgmtdev->max_read_request);
238 (max_read_request != mgmtdev->max_read_request)) {
241 mgmtdev->max_read_request = max_read_request;
243 max_read_request = mgmtdev->max_read_request;
246 &mgmtdev->max_wr_xactions);
252 (max_wr_xactions != mgmtdev->max_wr_xactions)) {
255 mgmtdev->max_wr_xactions = max_wr_xactions;
257 max_wr_xactions = mgmtdev->max_wr_xactions;
260 &mgmtdev->max_rd_xactions);
266 (max_rd_xactions != mgmtdev->max_rd_xactions)) {
269 mgmtdev->max_rd_xactions = max_rd_xactions;
271 max_rd_xactions = mgmtdev->max_rd_xactions;
273 mgmtdev->priority = devm_kcalloc(&pdev->dev,
274 mgmtdev->dma_channels,
275 sizeof(*mgmtdev->priority),
277 if (!mgmtdev->priority) {
282 mgmtdev->weight = devm_kcalloc(&pdev->dev,
283 mgmtdev->dma_channels,
284 sizeof(*mgmtdev->weight), GFP_KERNEL);
285 if (!mgmtdev->weight) {
290 rc = hidma_mgmt_setup(mgmtdev);
297 val = readl(mgmtdev->virtaddr + HIDMA_CFG_OFFSET);
299 writel(val, mgmtdev->virtaddr + HIDMA_CFG_OFFSET);
301 rc = hidma_mgmt_init_sys(mgmtdev);
309 mgmtdev->hw_version_major, mgmtdev->hw_version_minor,
310 &res->start, mgmtdev->dma_channels);
312 platform_set_drvdata(pdev, mgmtdev);