Lines Matching refs:chan
67 struct dma_chan *chan;
129 static void print_cb(struct ppc440spe_adma_chan *chan, void *block)
135 switch (chan->device->id) {
145 cdb, chan->device->id,
159 cb, chan->device->id,
173 static void print_cb_list(struct ppc440spe_adma_chan *chan,
177 print_cb(chan, iter->hw_desc);
232 struct ppc440spe_adma_chan *chan)
236 switch (chan->device->id) {
250 printk(KERN_ERR "Unsupported id %d in %s\n", chan->device->id,
442 * and/or Q to chan->pdest and/or chan->qdest as we have
523 struct ppc440spe_adma_chan *chan,
531 switch (chan->device->id) {
558 struct ppc440spe_adma_chan *chan, u32 mult_index,
564 switch (chan->device->id) {
602 struct ppc440spe_adma_chan *chan,
611 switch (chan->device->id) {
643 struct ppc440spe_adma_chan *chan,
649 switch (chan->device->id) {
678 struct ppc440spe_adma_chan *chan, u8 *qword)
682 switch (chan->device->id) {
721 static void ppc440spe_desc_set_link(struct ppc440spe_adma_chan *chan,
745 switch (chan->device->id) {
770 struct ppc440spe_adma_chan *chan)
890 ppc440spe_chan_get_current_descriptor(struct ppc440spe_adma_chan *chan);
891 static void ppc440spe_chan_append(struct ppc440spe_adma_chan *chan);
897 struct ppc440spe_adma_chan *chan)
901 u8 *p = chan->device->dma_desc_pool_virt;
905 switch (chan->device->id) {
909 dma_reg = chan->device->dma_reg;
913 (u32)chan->device->dma_desc_pool];
945 list_for_each_entry(iter, &chan->chain,
954 BUG_ON(&iter->chain_node == &chan->chain);
975 chan->device->id, rv);
982 xor_reg = chan->device->xor_reg;
1008 ppc440spe_chan_append(chan);
1016 static int ppc440spe_chan_is_busy(struct ppc440spe_adma_chan *chan)
1022 switch (chan->device->id) {
1025 dma_reg = chan->device->dma_reg;
1036 xor_reg = chan->device->xor_reg;
1048 struct ppc440spe_adma_chan *chan,
1051 struct xor_regs *xor_reg = chan->device->xor_reg;
1067 chan->hw_chain_inited = 1;
1074 static void ppc440spe_dma_put_desc(struct ppc440spe_adma_chan *chan,
1078 struct dma_regs *dma_reg = chan->device->dma_reg;
1084 chan_last_sub[chan->device->id] = desc;
1086 ADMA_LL_DBG(print_cb(chan, desc->hw_desc));
1094 static void ppc440spe_chan_append(struct ppc440spe_adma_chan *chan)
1104 switch (chan->device->id) {
1107 cur_desc = ppc440spe_chan_get_current_descriptor(chan);
1110 iter = chan_last_sub[chan->device->id];
1114 iter = chan_first_cdb[chan->device->id];
1116 ppc440spe_dma_put_desc(chan, iter);
1117 chan->hw_chain_inited = 1;
1125 list_for_each_entry_continue(iter, &chan->chain, chain_node) {
1126 ppc440spe_dma_put_desc(chan, iter);
1136 xor_reg = chan->device->xor_reg;
1151 ADMA_LL_DBG(print_cb_list(chan,
1173 ppc440spe_chan_get_current_descriptor(struct ppc440spe_adma_chan *chan)
1178 if (unlikely(!chan->hw_chain_inited))
1182 switch (chan->device->id) {
1185 dma_reg = chan->device->dma_reg;
1188 xor_reg = chan->device->xor_reg;
1197 static void ppc440spe_chan_run(struct ppc440spe_adma_chan *chan)
1201 switch (chan->device->id) {
1208 xor_reg = chan->device->xor_reg;
1221 static void ppc440spe_chan_start_null_xor(struct ppc440spe_adma_chan *chan);
1222 static int ppc440spe_adma_alloc_chan_resources(struct dma_chan *chan);
1316 * the operation given on this channel. It's assumed that 'chan' is
1318 * @chan: channel to use
1326 static int ppc440spe_adma_estimate(struct dma_chan *chan,
1349 if (cap == DMA_PQ && chan->chan_id == PPC440SPE_XOR_ID) {
1361 !ppc440spe_chan_is_busy(to_ppc440spe_adma_chan(chan)))
1400 if (dma_has_cap(cap, ref->chan->device->cap_mask)) {
1403 rank = ppc440spe_adma_estimate(ref->chan, cap, dst_lst,
1407 best_chan = ref->chan;
1445 struct ppc440spe_adma_chan *chan)
1463 struct ppc440spe_adma_chan *chan,
1488 struct ppc440spe_adma_chan *chan)
1499 if (list_is_last(&desc->chain_node, &chan->chain) ||
1500 desc->phys == ppc440spe_chan_get_current_descriptor(chan))
1503 if (chan->device->id != PPC440SPE_XOR_ID) {
1518 dev_dbg(chan->device->common.dev, "\tfree slot %llx: %d stride: %d\n",
1522 ppc440spe_adma_free_slots(desc, chan);
1533 static void __ppc440spe_adma_slot_cleanup(struct ppc440spe_adma_chan *chan)
1537 u32 current_desc = ppc440spe_chan_get_current_descriptor(chan);
1538 int busy = ppc440spe_chan_is_busy(chan);
1541 dev_dbg(chan->device->common.dev, "ppc440spe adma%d: %s\n",
1542 chan->device->id, __func__);
1554 list_for_each_entry_safe(iter, _iter, &chan->chain,
1556 dev_dbg(chan->device->common.dev, "\tcookie: %d slot: %d "
1560 ppc440spe_desc_get_link(iter, chan), current_desc,
1578 if (busy || ppc440spe_desc_get_link(iter, chan)) {
1611 &chan->chain, chain_node) {
1614 grp_iter, chan, cookie);
1618 grp_iter, chan);
1622 chan->common.completed_cookie = cookie;
1642 cookie = ppc440spe_adma_run_tx_complete_actions(iter, chan,
1645 if (ppc440spe_adma_clean_slot(iter, chan))
1652 chan->common.completed_cookie = cookie;
1663 struct ppc440spe_adma_chan *chan = from_tasklet(chan, t, irq_tasklet);
1665 spin_lock_nested(&chan->lock, SINGLE_DEPTH_NESTING);
1666 __ppc440spe_adma_slot_cleanup(chan);
1667 spin_unlock(&chan->lock);
1673 static void ppc440spe_adma_slot_cleanup(struct ppc440spe_adma_chan *chan)
1675 spin_lock_bh(&chan->lock);
1676 __ppc440spe_adma_slot_cleanup(chan);
1677 spin_unlock_bh(&chan->lock);
1684 struct ppc440spe_adma_chan *chan, int num_slots,
1701 iter = chan->last_used;
1703 iter = list_entry(&chan->all_slots,
1706 list_for_each_entry_safe_continue(iter, _iter, &chan->all_slots,
1749 chan->last_used = last_used;
1757 tasklet_schedule(&chan->irq_tasklet);
1764 static int ppc440spe_adma_alloc_chan_resources(struct dma_chan *chan)
1772 ppc440spe_chan = to_ppc440spe_adma_chan(chan);
1774 chan->chan_id = ppc440spe_chan->device->id;
1794 dma_async_tx_descriptor_init(&slot->async_tx, chan);
1879 static void ppc440spe_adma_check_threshold(struct ppc440spe_adma_chan *chan)
1881 dev_dbg(chan->device->common.dev, "ppc440spe adma%d: pending: %d\n",
1882 chan->device->id, chan->pending);
1884 if (chan->pending >= PPC440SPE_ADMA_THRESHOLD) {
1885 chan->pending = 0;
1886 ppc440spe_chan_append(chan);
1898 struct ppc440spe_adma_chan *chan = to_ppc440spe_adma_chan(tx->chan);
1910 spin_lock_bh(&chan->lock);
1913 if (unlikely(list_empty(&chan->chain))) {
1915 list_splice_init(&sw_desc->group_list, &chan->chain);
1916 chan_first_cdb[chan->device->id] = group_start;
1919 old_chain_tail = list_entry(chan->chain.prev,
1925 ppc440spe_desc_set_link(chan, old_chain_tail, group_start);
1929 chan->pending += slot_cnt / slots_per_op;
1930 ppc440spe_adma_check_threshold(chan);
1931 spin_unlock_bh(&chan->lock);
1933 dev_dbg(chan->device->common.dev,
1935 chan->device->id, __func__,
1945 struct dma_chan *chan, unsigned long flags)
1951 ppc440spe_chan = to_ppc440spe_adma_chan(chan);
1976 struct dma_chan *chan, dma_addr_t dma_dest,
1983 ppc440spe_chan = to_ppc440spe_adma_chan(chan);
2017 struct dma_chan *chan, dma_addr_t dma_dest,
2025 ppc440spe_chan = to_ppc440spe_adma_chan(chan);
2100 struct ppc440spe_adma_chan *chan;
2104 chan = to_ppc440spe_adma_chan(sw_desc->async_tx.chan);
2123 ppc440spe_desc_set_dest_addr(iter, chan,
2125 ppc440spe_desc_set_dest_addr(iter, chan, 0, dst[1], 1);
2126 ppc440spe_desc_set_src_addr(iter, chan, 0, DMA_CUED_XOR_HB,
2147 ppc440spe_desc_set_src_addr(iter, chan, 0,
2149 ppc440spe_desc_set_dest_addr(iter, chan,
2152 ppc440spe_desc_set_src_mult(iter, chan, DMA_CUED_MULT1_OFF,
2186 struct ppc440spe_adma_chan *chan;
2190 chan = to_ppc440spe_adma_chan(sw_desc->async_tx.chan);
2206 ppc440spe_desc_set_dest_addr(iter, chan, DMA_CUED_XOR_BASE,
2208 ppc440spe_desc_set_dest_addr(iter, chan, 0,
2210 ppc440spe_desc_set_src_addr(iter, chan, 0, DMA_CUED_XOR_HB,
2232 ppc440spe_desc_set_src_addr(iter, chan, 0, DMA_CUED_XOR_HB,
2234 ppc440spe_desc_set_dest_addr(iter, chan, DMA_CUED_XOR_BASE,
2236 ppc440spe_desc_set_src_mult(iter, chan, DMA_CUED_MULT1_OFF,
2257 ppc440spe_desc_set_src_addr(iter, chan, 0, DMA_CUED_XOR_HB,
2259 ppc440spe_desc_set_dest_addr(iter, chan, DMA_CUED_XOR_BASE,
2261 ppc440spe_desc_set_src_mult(iter, chan, DMA_CUED_MULT1_OFF,
2508 struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
2516 ppc440spe_chan = to_ppc440spe_adma_chan(chan);
2584 struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
2593 ppc440spe_chan = to_ppc440spe_adma_chan(chan);
2635 struct ppc440spe_adma_chan *chan;
2638 chan = to_ppc440spe_adma_chan(iter->async_tx.chan);
2647 ppc440spe_desc_set_dest_addr(iter, chan, 0,
2649 ppc440spe_desc_set_src_addr(iter, chan, 0, 0, pdest);
2658 struct ppc440spe_adma_chan *chan;
2663 chan = to_ppc440spe_adma_chan(iter->async_tx.chan);
2679 ppc440spe_desc_set_dest_addr(iter, chan, 0,
2681 ppc440spe_desc_set_src_addr(iter, chan, 0, 0, qdest);
2735 struct ppc440spe_adma_chan *chan;
2738 chan = to_ppc440spe_adma_chan(iter->async_tx.chan);
2739 ppc440spe_desc_set_src_addr(iter, chan, 0,
2745 ppc440spe_desc_set_src_mult(iter, chan,
2763 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
2774 tx = ppc440spe_adma_prep_dma_pqzero_sum(chan, pq, &src[1],
2786 struct ppc440spe_adma_chan *chan;
2790 chan = to_ppc440spe_adma_chan(sw_desc->async_tx.chan);
2792 switch (chan->device->id) {
2799 chan, 0, addr, index);
2804 chan, 0, addr, index);
2810 struct ppc440spe_adma_chan *chan, dma_addr_t addr)
2816 ppc440spe_desc_set_dest_addr(iter, chan, DMA_CUED_XOR_BASE, addr, 0);
2819 ppc440spe_desc_set_src_addr(iter, chan, 0, DMA_CUED_XOR_HB, addr);
2822 ppc440spe_desc_set_src_mult(iter, chan, DMA_CUED_MULT1_OFF,
2834 struct ppc440spe_adma_chan *chan;
2839 chan = to_ppc440spe_adma_chan(sw_desc->async_tx.chan);
2854 switch (chan->device->id) {
2872 ppc440spe_desc_set_dest_addr(iter, chan,
2878 ppc440spe_desc_set_dest_addr(iter, chan,
2880 ppc440spe_desc_set_dest_addr(iter, chan,
2894 ppc440spe_adma_pq_zero_op(iter, chan,
2902 ppc440spe_adma_pq_zero_op(iter, chan,
2925 ppc440spe_desc_set_dest_addr(iter, chan,
2932 ppc440spe_desc_set_dest_addr(iter, chan,
2948 iter, chan,
2958 iter, chan,
2962 iter, chan,
2990 ppc440spe_desc_set_dest_addr(iter, chan,
3004 chan, qpath, qaddr, 0);
3024 struct ppc440spe_adma_chan *chan;
3028 chan = to_ppc440spe_adma_chan(sw_desc->async_tx.chan);
3050 ppc440spe_desc_set_dest_addr(iter, chan,
3052 ppc440spe_desc_set_dest_addr(iter, chan,
3062 ppc440spe_desc_set_dest_addr(iter, chan,
3071 ppc440spe_desc_set_src_addr(end, chan, 0, 0, addr ? addr : paddr);
3076 ppc440spe_desc_set_src_addr(end, chan, 0, 0, qaddr);
3099 struct ppc440spe_adma_chan *chan;
3103 chan = to_ppc440spe_adma_chan(sw_desc->async_tx.chan);
3105 switch (chan->device->id) {
3171 ppc440spe_desc_set_src_addr(iter, chan, 0, haddr, addr);
3180 ppc440spe_desc_set_src_addr(iter, chan, 0,
3209 struct ppc440spe_adma_chan *chan;
3211 chan = to_ppc440spe_adma_chan(sw_desc->async_tx.chan);
3215 ppc440spe_desc_set_src_addr(sw_desc, chan, index, 0, addr);
3450 struct ppc440spe_adma_chan *chan;
3454 chan = to_ppc440spe_adma_chan(sw_desc->async_tx.chan);
3456 switch (chan->device->id) {
3500 ppc440spe_desc_set_src_mult(iter, chan,
3507 ppc440spe_desc_set_src_mult(iter1, chan,
3532 static void ppc440spe_adma_free_chan_resources(struct dma_chan *chan)
3538 ppc440spe_chan = to_ppc440spe_adma_chan(chan);
3569 * @chan: ADMA channel handle
3573 static enum dma_status ppc440spe_adma_tx_status(struct dma_chan *chan,
3579 ppc440spe_chan = to_ppc440spe_adma_chan(chan);
3580 ret = dma_cookie_status(chan, cookie, txstate);
3586 return dma_cookie_status(chan, cookie, txstate);
3594 struct ppc440spe_adma_chan *chan = data;
3596 dev_dbg(chan->device->common.dev,
3597 "ppc440spe adma%d: %s\n", chan->device->id, __func__);
3599 tasklet_schedule(&chan->irq_tasklet);
3600 ppc440spe_adma_device_clear_eot_status(chan);
3611 struct ppc440spe_adma_chan *chan = data;
3613 dev_dbg(chan->device->common.dev,
3614 "ppc440spe adma%d: %s\n", chan->device->id, __func__);
3616 tasklet_schedule(&chan->irq_tasklet);
3617 ppc440spe_adma_device_clear_eot_status(chan);
3633 static void ppc440spe_adma_issue_pending(struct dma_chan *chan)
3637 ppc440spe_chan = to_ppc440spe_adma_chan(chan);
3653 static void ppc440spe_chan_start_null_xor(struct ppc440spe_adma_chan *chan)
3659 dev_dbg(chan->device->common.dev,
3660 "ppc440spe adma%d: %s\n", chan->device->id, __func__);
3662 spin_lock_bh(&chan->lock);
3664 sw_desc = ppc440spe_adma_alloc_slots(chan, slot_cnt, slots_per_op);
3667 list_splice_init(&sw_desc->group_list, &chan->chain);
3676 chan->common.completed_cookie = cookie - 1;
3679 BUG_ON(ppc440spe_chan_is_busy(chan));
3682 ppc440spe_chan_set_first_xor_descriptor(chan, sw_desc);
3685 ppc440spe_chan_run(chan);
3689 chan->device->id);
3690 spin_unlock_bh(&chan->lock);
3699 static int ppc440spe_test_raid6(struct ppc440spe_adma_chan *chan)
3714 spin_lock_bh(&chan->lock);
3715 sw_desc = ppc440spe_adma_alloc_slots(chan, 1, 1);
3720 ppc440spe_desc_set_byte_count(iter, chan, PAGE_SIZE);
3725 spin_unlock_bh(&chan->lock);
3728 spin_unlock_bh(&chan->lock);
3732 dma_addr = dma_map_page(chan->device->dev, pg, 0,
3749 ppc440spe_adma_issue_pending(&chan->common);
3865 struct ppc440spe_adma_chan *chan,
3897 0, dev_driver_string(adev->dev), chan);
3915 chan);
3960 free_irq(adev->irq, chan);
3972 struct ppc440spe_adma_chan *chan)
3990 free_irq(adev->irq, chan);
3993 free_irq(adev->err_irq, chan);
4009 struct ppc440spe_adma_chan *chan;
4127 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
4128 if (!chan) {
4134 spin_lock_init(&chan->lock);
4135 INIT_LIST_HEAD(&chan->chain);
4136 INIT_LIST_HEAD(&chan->all_slots);
4137 chan->device = adev;
4138 chan->common.device = &adev->common;
4139 dma_cookie_init(&chan->common);
4140 list_add_tail(&chan->common.device_node, &adev->common.channels);
4141 tasklet_setup(&chan->irq_tasklet, ppc440spe_adma_tasklet);
4147 chan->pdest_page = alloc_page(GFP_KERNEL);
4148 chan->qdest_page = alloc_page(GFP_KERNEL);
4149 if (!chan->pdest_page ||
4150 !chan->qdest_page) {
4151 if (chan->pdest_page)
4152 __free_page(chan->pdest_page);
4153 if (chan->qdest_page)
4154 __free_page(chan->qdest_page);
4158 chan->pdest = dma_map_page(&ofdev->dev, chan->pdest_page, 0,
4160 chan->qdest = dma_map_page(&ofdev->dev, chan->qdest_page, 0,
4166 ref->chan = &chan->common;
4175 ret = ppc440spe_adma_setup_irqs(adev, chan, &initcode);
4191 ppc440spe_adma_release_irqs(adev, chan);
4194 if (chan == to_ppc440spe_adma_chan(ref->chan)) {
4201 dma_unmap_page(&ofdev->dev, chan->pdest,
4203 dma_unmap_page(&ofdev->dev, chan->qdest,
4205 __free_page(chan->pdest_page);
4206 __free_page(chan->qdest_page);
4209 kfree(chan);
4238 struct dma_chan *chan, *_chan;
4247 list_for_each_entry_safe(chan, _chan, &adev->common.channels,
4249 ppc440spe_chan = to_ppc440spe_adma_chan(chan);
4263 to_ppc440spe_adma_chan(ref->chan)) {
4268 list_del(&chan->device_node);