Lines Matching refs:ch
185 struct moxart_chan *ch = to_moxart_dma_chan(chan);
190 dev_dbg(chan2dev(chan), "%s: ch=%p\n", __func__, ch);
192 spin_lock_irqsave(&ch->vc.lock, flags);
194 if (ch->desc) {
195 moxart_dma_desc_free(&ch->desc->vd);
196 ch->desc = NULL;
199 ctrl = readl(ch->base + REG_OFF_CTRL);
201 writel(ctrl, ch->base + REG_OFF_CTRL);
203 vchan_get_all_descriptors(&ch->vc, &head);
204 spin_unlock_irqrestore(&ch->vc.lock, flags);
205 vchan_dma_desc_free_list(&ch->vc, &head);
213 struct moxart_chan *ch = to_moxart_dma_chan(chan);
216 ch->cfg = *cfg;
218 ctrl = readl(ch->base + REG_OFF_CTRL);
223 switch (ch->cfg.src_addr_width) {
226 if (ch->cfg.direction != DMA_MEM_TO_DEV)
233 if (ch->cfg.direction != DMA_MEM_TO_DEV)
240 if (ch->cfg.direction != DMA_MEM_TO_DEV)
249 if (ch->cfg.direction == DMA_MEM_TO_DEV) {
252 ctrl |= (ch->line_reqno << 16 &
257 ctrl |= (ch->line_reqno << 24 &
261 writel(ctrl, ch->base + REG_OFF_CTRL);
271 struct moxart_chan *ch = to_moxart_dma_chan(chan);
286 dev_addr = ch->cfg.src_addr;
287 dev_width = ch->cfg.src_addr_width;
289 dev_addr = ch->cfg.dst_addr;
290 dev_width = ch->cfg.dst_addr_width;
324 ch->error = 0;
326 return vchan_tx_prep(&ch->vc, &d->vd, tx_flags);
334 struct moxart_chan *ch;
340 ch = to_moxart_dma_chan(chan);
341 ch->line_reqno = dma_spec->args[0];
348 struct moxart_chan *ch = to_moxart_dma_chan(chan);
351 __func__, ch->ch_num);
352 ch->allocated = 1;
359 struct moxart_chan *ch = to_moxart_dma_chan(chan);
361 vchan_free_chan_resources(&ch->vc);
364 __func__, ch->ch_num);
365 ch->allocated = 0;
368 static void moxart_dma_set_params(struct moxart_chan *ch, dma_addr_t src_addr,
371 writel(src_addr, ch->base + REG_OFF_ADDRESS_SOURCE);
372 writel(dst_addr, ch->base + REG_OFF_ADDRESS_DEST);
375 static void moxart_set_transfer_params(struct moxart_chan *ch, unsigned int len)
377 struct moxart_desc *d = ch->desc;
386 writel(d->dma_cycles, ch->base + REG_OFF_CYCLES);
388 dev_dbg(chan2dev(&ch->vc.chan), "%s: set %u DMA cycles (len=%u)\n",
392 static void moxart_start_dma(struct moxart_chan *ch)
396 ctrl = readl(ch->base + REG_OFF_CTRL);
398 writel(ctrl, ch->base + REG_OFF_CTRL);
401 static void moxart_dma_start_sg(struct moxart_chan *ch, unsigned int idx)
403 struct moxart_desc *d = ch->desc;
404 struct moxart_sg *sg = ch->desc->sg + idx;
406 if (ch->desc->dma_dir == DMA_MEM_TO_DEV)
407 moxart_dma_set_params(ch, sg->addr, d->dev_addr);
408 else if (ch->desc->dma_dir == DMA_DEV_TO_MEM)
409 moxart_dma_set_params(ch, d->dev_addr, sg->addr);
411 moxart_set_transfer_params(ch, sg->len);
413 moxart_start_dma(ch);
418 struct moxart_chan *ch = to_moxart_dma_chan(chan);
421 vd = vchan_next_desc(&ch->vc);
424 ch->desc = NULL;
430 ch->desc = to_moxart_dma_desc(&vd->tx);
431 ch->sgidx = 0;
433 moxart_dma_start_sg(ch, 0);
438 struct moxart_chan *ch = to_moxart_dma_chan(chan);
441 spin_lock_irqsave(&ch->vc.lock, flags);
442 if (vchan_issue_pending(&ch->vc) && !ch->desc)
444 spin_unlock_irqrestore(&ch->vc.lock, flags);
459 static size_t moxart_dma_desc_size_in_flight(struct moxart_chan *ch)
464 size = moxart_dma_desc_size(ch->desc, ch->sgidx);
465 cycles = readl(ch->base + REG_OFF_CYCLES);
466 completed_cycles = (ch->desc->dma_cycles - cycles);
467 size -= completed_cycles << es_bytes[ch->desc->es];
469 dev_dbg(chan2dev(&ch->vc.chan), "%s: size=%zu\n", __func__, size);
478 struct moxart_chan *ch = to_moxart_dma_chan(chan);
489 spin_lock_irqsave(&ch->vc.lock, flags);
490 vd = vchan_find_desc(&ch->vc, cookie);
494 } else if (ch->desc && ch->desc->vd.tx.cookie == cookie) {
495 txstate->residue = moxart_dma_desc_size_in_flight(ch);
497 spin_unlock_irqrestore(&ch->vc.lock, flags);
499 if (ch->error)
522 struct moxart_chan *ch = &mc->slave_chans[0];
526 dev_dbg(chan2dev(&ch->vc.chan), "%s\n", __func__);
528 for (i = 0; i < APB_DMA_MAX_CHANNEL; i++, ch++) {
529 if (!ch->allocated)
532 ctrl = readl(ch->base + REG_OFF_CTRL);
534 dev_dbg(chan2dev(&ch->vc.chan), "%s: ch=%p ch->base=%p ctrl=%x\n",
535 __func__, ch, ch->base, ctrl);
539 if (ch->desc) {
540 spin_lock(&ch->vc.lock);
541 if (++ch->sgidx < ch->desc->sglen) {
542 moxart_dma_start_sg(ch, ch->sgidx);
544 vchan_cookie_complete(&ch->desc->vd);
545 moxart_dma_start_desc(&ch->vc.chan);
547 spin_unlock(&ch->vc.lock);
553 ch->error = 1;
556 writel(ctrl, ch->base + REG_OFF_CTRL);
569 struct moxart_chan *ch;
592 ch = &mdc->slave_chans[0];
593 for (i = 0; i < APB_DMA_MAX_CHANNEL; i++, ch++) {
594 ch->ch_num = i;
595 ch->base = dma_base_addr + i * REG_OFF_CHAN_SIZE;
596 ch->allocated = 0;
598 ch->vc.desc_free = moxart_dma_desc_free;
599 vchan_init(&ch->vc, &mdc->dma_slave);
601 dev_dbg(dev, "%s: chs[%d]: ch->ch_num=%u ch->base=%p\n",
602 __func__, i, ch->ch_num, ch->base);