Lines Matching refs:mcf_edma
19 struct fsl_edma_engine *mcf_edma = dev_id;
20 struct edma_regs *regs = &mcf_edma->regs;
30 for (ch = 0; ch < mcf_edma->n_chans; ch++) {
33 fsl_edma_tx_chan_handler(&mcf_edma->chans[ch]);
42 struct fsl_edma_engine *mcf_edma = dev_id;
43 struct edma_regs *regs = &mcf_edma->regs;
52 fsl_edma_disable_request(&mcf_edma->chans[ch]);
54 fsl_edma_err_chan_handler(&mcf_edma->chans[ch]);
64 fsl_edma_disable_request(&mcf_edma->chans[ch]);
66 mcf_edma->chans[ch].status = DMA_ERROR;
67 mcf_edma->chans[ch].idle = true;
75 struct fsl_edma_engine *mcf_edma)
86 ret |= request_irq(i, mcf_edma_tx_handler, 0, "eDMA", mcf_edma);
96 ret |= request_irq(i, mcf_edma_tx_handler, 0, "eDMA", mcf_edma);
103 0, "eDMA", mcf_edma);
111 0, "eDMA", mcf_edma);
120 struct fsl_edma_engine *mcf_edma)
129 free_irq(irq, mcf_edma);
136 free_irq(irq, mcf_edma);
141 free_irq(irq, mcf_edma);
145 free_irq(irq, mcf_edma);
156 struct fsl_edma_engine *mcf_edma;
173 mcf_edma = devm_kzalloc(&pdev->dev, struct_size(mcf_edma, chans, chans),
175 if (!mcf_edma)
178 mcf_edma->n_chans = chans;
181 mcf_edma->drvdata = &mcf_data;
182 mcf_edma->big_endian = 1;
184 mutex_init(&mcf_edma->fsl_edma_mutex);
186 mcf_edma->membase = devm_platform_ioremap_resource(pdev, 0);
187 if (IS_ERR(mcf_edma->membase))
188 return PTR_ERR(mcf_edma->membase);
190 fsl_edma_setup_regs(mcf_edma);
191 regs = &mcf_edma->regs;
193 INIT_LIST_HEAD(&mcf_edma->dma_dev.channels);
194 for (i = 0; i < mcf_edma->n_chans; i++) {
195 struct fsl_edma_chan *mcf_chan = &mcf_edma->chans[i];
197 mcf_chan->edma = mcf_edma;
202 vchan_init(&mcf_chan->vchan, &mcf_edma->dma_dev);
203 mcf_chan->tcd = mcf_edma->membase + EDMA_TCD
211 ret = mcf_edma->drvdata->setup_irq(pdev, mcf_edma);
215 dma_cap_set(DMA_PRIVATE, mcf_edma->dma_dev.cap_mask);
216 dma_cap_set(DMA_SLAVE, mcf_edma->dma_dev.cap_mask);
217 dma_cap_set(DMA_CYCLIC, mcf_edma->dma_dev.cap_mask);
219 mcf_edma->dma_dev.dev = &pdev->dev;
220 mcf_edma->dma_dev.device_alloc_chan_resources =
222 mcf_edma->dma_dev.device_free_chan_resources =
224 mcf_edma->dma_dev.device_config = fsl_edma_slave_config;
225 mcf_edma->dma_dev.device_prep_dma_cyclic =
227 mcf_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg;
228 mcf_edma->dma_dev.device_tx_status = fsl_edma_tx_status;
229 mcf_edma->dma_dev.device_pause = fsl_edma_pause;
230 mcf_edma->dma_dev.device_resume = fsl_edma_resume;
231 mcf_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all;
232 mcf_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending;
234 mcf_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS;
235 mcf_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS;
236 mcf_edma->dma_dev.directions =
239 mcf_edma->dma_dev.filter.fn = mcf_edma_filter_fn;
240 mcf_edma->dma_dev.filter.map = pdata->slave_map;
241 mcf_edma->dma_dev.filter.mapcnt = pdata->slavecnt;
243 platform_set_drvdata(pdev, mcf_edma);
245 ret = dma_async_device_register(&mcf_edma->dma_dev);
260 struct fsl_edma_engine *mcf_edma = platform_get_drvdata(pdev);
262 mcf_edma_irq_free(pdev, mcf_edma);
263 fsl_edma_cleanup_vchan(&mcf_edma->dma_dev);
264 dma_async_device_unregister(&mcf_edma->dma_dev);