Lines Matching refs:sdma
3 // drivers/dma/imx-sdma.c
314 * struct sdma_context_data - sdma context specific to a channel
401 * @desc: sdma description including vd and other special member
402 * @sdma: pointer to the SDMA engine for this channel
425 * @data: specific sdma interface structure
440 struct sdma_engine *sdma;
508 * ecspi ERR009165 fixed should be done in sdma script
667 { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, },
668 { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, },
669 { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, },
670 { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
671 { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
672 { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
673 { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, },
674 { .compatible = "fsl,imx6ul-sdma", .data = &sdma_imx6ul, },
675 { .compatible = "fsl,imx8mq-sdma", .data = &sdma_imx8mq, },
685 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
687 u32 chnenbl0 = sdma->drvdata->chnenbl0;
694 struct sdma_engine *sdma = sdmac->sdma;
701 evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR);
702 mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR);
703 dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR);
720 writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR);
721 writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR);
722 writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR);
727 static int is_sdma_channel_enabled(struct sdma_engine *sdma, int channel)
729 return !!(readl(sdma->regs + SDMA_H_STATSTOP) & BIT(channel));
732 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
734 writel(BIT(channel), sdma->regs + SDMA_H_START);
740 static int sdma_run_channel0(struct sdma_engine *sdma)
745 sdma_enable_channel(sdma, 0);
747 ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP,
750 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
753 reg = readl(sdma->regs + SDMA_H_CONFIG);
756 writel_relaxed(reg, sdma->regs + SDMA_H_CONFIG);
762 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
765 struct sdma_buffer_descriptor *bd0 = sdma->bd0;
771 buf_virt = dma_alloc_coherent(sdma->dev, size, &buf_phys, GFP_KERNEL);
775 spin_lock_irqsave(&sdma->channel_0_lock, flags);
785 ret = sdma_run_channel0(sdma);
787 spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
789 dma_free_coherent(sdma->dev, size, buf_virt, buf_phys);
796 struct sdma_engine *sdma = sdmac->sdma;
799 u32 chnenbl = chnenbl_ofs(sdma, event);
801 val = readl_relaxed(sdma->regs + chnenbl);
803 writel_relaxed(val, sdma->regs + chnenbl);
807 val = readl_relaxed(sdma->regs + SDMA_DONE0_CONFIG);
810 writel_relaxed(val, sdma->regs + SDMA_DONE0_CONFIG);
816 struct sdma_engine *sdma = sdmac->sdma;
818 u32 chnenbl = chnenbl_ofs(sdma, event);
821 val = readl_relaxed(sdma->regs + chnenbl);
823 writel_relaxed(val, sdma->regs + chnenbl);
835 struct sdma_engine *sdma = sdmac->sdma;
846 sdma->channel_control[channel].base_bd_ptr = desc->bd_phys;
847 sdma->channel_control[channel].current_bd_ptr = desc->bd_phys;
848 sdma_enable_channel(sdma, sdmac->channel);
906 if (sdmac->desc && !is_sdma_channel_enabled(sdmac->sdma, sdmac->channel)) {
907 dev_warn(sdmac->sdma->dev, "restart cyclic channel %d\n", sdmac->channel);
908 sdma_enable_channel(sdmac->sdma, sdmac->channel);
939 struct sdma_engine *sdma = dev_id;
942 stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
943 writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
949 struct sdma_channel *sdmac = &sdma->channel[channel];
980 struct sdma_engine *sdma = sdmac->sdma;
996 emi_2_emi = sdma->script_addrs->ap_2_ap_addr;
999 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
1000 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
1003 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
1004 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
1007 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
1008 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
1011 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
1012 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
1015 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
1016 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
1019 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
1022 if (sdmac->sdma->drvdata->ecspi_fixed) {
1023 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
1025 emi_2_per = sdma->script_addrs->mcu_2_ecspi_addr;
1033 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
1034 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
1037 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr;
1038 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr;
1047 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
1048 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
1051 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
1052 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
1053 per_2_per = sdma->script_addrs->per_2_per_addr;
1057 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
1058 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
1059 per_2_per = sdma->script_addrs->per_2_per_addr;
1062 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
1063 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
1066 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
1069 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
1070 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
1073 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
1076 per_2_emi = sdma->script_addrs->sai_2_mcu_addr;
1077 emi_2_per = sdma->script_addrs->mcu_2_sai_addr;
1080 emi_2_per = sdma->script_addrs->hdmi_dma_addr;
1084 dev_err(sdma->dev, "Unsupported transfer type %d\n",
1099 struct sdma_engine *sdma = sdmac->sdma;
1102 struct sdma_context_data *context = sdma->context;
1103 struct sdma_buffer_descriptor *bd0 = sdma->bd0;
1119 dev_dbg(sdma->dev, "load_address = %d\n", load_address);
1120 dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level);
1121 dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
1122 dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
1123 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]);
1124 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]);
1126 spin_lock_irqsave(&sdma->channel_0_lock, flags);
1148 bd0->buffer_addr = sdma->context_phys;
1150 ret = sdma_run_channel0(sdma);
1152 spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
1165 struct sdma_engine *sdma = sdmac->sdma;
1168 writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
1226 struct sdma_engine *sdma = sdmac->sdma;
1253 if (sdmac->per_address2 >= sdma->spba_start_addr &&
1254 sdmac->per_address2 <= sdma->spba_end_addr)
1257 if (sdmac->per_address >= sdma->spba_start_addr &&
1258 sdmac->per_address <= sdma->spba_end_addr)
1348 struct sdma_engine *sdma = sdmac->sdma;
1356 writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
1361 static int sdma_request_channel0(struct sdma_engine *sdma)
1365 sdma->bd0 = dma_alloc_coherent(sdma->dev, PAGE_SIZE, &sdma->bd0_phys,
1367 if (!sdma->bd0) {
1372 sdma->channel_control[0].base_bd_ptr = sdma->bd0_phys;
1373 sdma->channel_control[0].current_bd_ptr = sdma->bd0_phys;
1375 sdma_set_channel_priority(&sdma->channel[0], MXC_SDMA_DEFAULT_PRIORITY);
1388 desc->bd = dma_alloc_coherent(desc->sdmac->sdma->dev, bd_size,
1402 dma_free_coherent(desc->sdmac->sdma->dev, bd_size, desc->bd,
1431 dev_dbg(sdmac->sdma->dev, "MEMCPY in case?\n");
1460 ret = clk_enable(sdmac->sdma->clk_ipg);
1463 ret = clk_enable(sdmac->sdma->clk_ahb);
1474 clk_disable(sdmac->sdma->clk_ahb);
1476 clk_disable(sdmac->sdma->clk_ipg);
1483 struct sdma_engine *sdma = sdmac->sdma;
1498 clk_disable(sdma->clk_ipg);
1499 clk_disable(sdma->clk_ahb);
1507 if (!sdmac->sdma->fw_loaded && sdmac->is_ram_script) {
1508 dev_warn_once(sdmac->sdma->dev, "sdma firmware not ready!\n");
1552 struct sdma_engine *sdma = sdmac->sdma;
1562 dev_dbg(sdma->dev, "memcpy: %pad->%pad, len=%zu, channel=%d.\n",
1592 dev_dbg(sdma->dev, "entry %d: count: %zd dma: 0x%x %s%s\n",
1609 struct sdma_engine *sdma = sdmac->sdma;
1621 dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
1633 dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
1670 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
1693 struct sdma_engine *sdma = sdmac->sdma;
1699 dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1715 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %zu > %d\n",
1742 dev_dbg(sdma->dev, "entry %d: count: %zu dma: %#llx %s%s\n",
1801 struct sdma_engine *sdma = sdmac->sdma;
1808 dev_err(sdma->dev, "Invalid peripheral size %zu, expected %zu\n",
1822 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
1827 if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events)
1892 static void sdma_add_scripts(struct sdma_engine *sdma,
1896 s32 *saddr_arr = (u32 *)sdma->script_addrs;
1900 if (!sdma->script_number)
1901 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1903 if (sdma->script_number > sizeof(struct sdma_script_start_addrs)
1905 dev_err(sdma->dev,
1907 sdma->script_number);
1911 for (i = 0; i < sdma->script_number; i++)
1918 * script, both uart ram/rom scripts are present in newer sdma
1921 if (sdma->script_number >= SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3) {
1923 sdma->script_addrs->uart_2_mcu_addr = addr->uart_2_mcu_rom_addr;
1925 sdma->script_addrs->uartsh_2_mcu_addr = addr->uartsh_2_mcu_rom_addr;
1931 struct sdma_engine *sdma = context;
1937 dev_info(sdma->dev, "external firmware not found, using ROM firmware\n");
1953 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1956 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2;
1959 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3;
1962 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4;
1965 dev_err(sdma->dev, "unknown firmware version\n");
1972 clk_enable(sdma->clk_ipg);
1973 clk_enable(sdma->clk_ahb);
1975 sdma_load_script(sdma, ram_code,
1978 clk_disable(sdma->clk_ipg);
1979 clk_disable(sdma->clk_ahb);
1981 sdma_add_scripts(sdma, addr);
1983 sdma->fw_loaded = true;
1985 dev_info(sdma->dev, "loaded firmware %d.%d\n",
1995 static int sdma_event_remap(struct sdma_engine *sdma)
1997 struct device_node *np = sdma->dev->of_node;
2001 char propname[] = "fsl,sdma-event-remap";
2011 dev_dbg(sdma->dev, "no event needs to be remapped\n");
2014 dev_err(sdma->dev, "the property %s must modulo %d\n",
2022 dev_err(sdma->dev, "failed to get gpr regmap\n");
2030 dev_err(sdma->dev, "failed to read property %s index %d\n",
2037 dev_err(sdma->dev, "failed to read property %s index %d\n",
2044 dev_err(sdma->dev, "failed to read property %s index %d\n",
2059 static int sdma_get_firmware(struct sdma_engine *sdma,
2065 FW_ACTION_UEVENT, fw_name, sdma->dev,
2066 GFP_KERNEL, sdma, sdma_load_firmware);
2071 static int sdma_init(struct sdma_engine *sdma)
2076 ret = clk_enable(sdma->clk_ipg);
2079 ret = clk_enable(sdma->clk_ahb);
2083 if (sdma->drvdata->check_ratio &&
2084 (clk_get_rate(sdma->clk_ahb) == clk_get_rate(sdma->clk_ipg)))
2085 sdma->clk_ratio = 1;
2088 writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
2090 sdma->channel_control = dma_alloc_coherent(sdma->dev,
2095 if (!sdma->channel_control) {
2100 sdma->context = (void *)sdma->channel_control +
2102 sdma->context_phys = ccb_phys +
2106 for (i = 0; i < sdma->drvdata->num_events; i++)
2107 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i));
2111 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
2113 ret = sdma_request_channel0(sdma);
2117 sdma_config_ownership(&sdma->channel[0], false, true, false);
2120 writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
2123 if (sdma->clk_ratio)
2124 writel_relaxed(SDMA_H_CONFIG_ACR, sdma->regs + SDMA_H_CONFIG);
2126 writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
2128 writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
2131 sdma_set_channel_priority(&sdma->channel[0], 7);
2133 clk_disable(sdma->clk_ipg);
2134 clk_disable(sdma->clk_ahb);
2139 clk_disable(sdma->clk_ahb);
2141 clk_disable(sdma->clk_ipg);
2142 dev_err(sdma->dev, "initialisation failed with %d\n", ret);
2163 struct sdma_engine *sdma = ofdma->of_dma_data;
2164 dma_cap_mask_t mask = sdma->dma_device.cap_mask;
2195 struct sdma_engine *sdma;
2202 sdma = devm_kzalloc(&pdev->dev, sizeof(*sdma), GFP_KERNEL);
2203 if (!sdma)
2206 spin_lock_init(&sdma->channel_0_lock);
2208 sdma->dev = &pdev->dev;
2209 sdma->drvdata = of_device_get_match_data(sdma->dev);
2215 sdma->regs = devm_platform_ioremap_resource(pdev, 0);
2216 if (IS_ERR(sdma->regs))
2217 return PTR_ERR(sdma->regs);
2219 sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2220 if (IS_ERR(sdma->clk_ipg))
2221 return PTR_ERR(sdma->clk_ipg);
2223 sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
2224 if (IS_ERR(sdma->clk_ahb))
2225 return PTR_ERR(sdma->clk_ahb);
2227 ret = clk_prepare(sdma->clk_ipg);
2231 ret = clk_prepare(sdma->clk_ahb);
2236 dev_name(&pdev->dev), sdma);
2240 sdma->irq = irq;
2242 sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
2243 if (!sdma->script_addrs) {
2249 saddr_arr = (s32 *)sdma->script_addrs;
2250 for (i = 0; i < sizeof(*sdma->script_addrs) / sizeof(s32); i++)
2253 dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
2254 dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
2255 dma_cap_set(DMA_MEMCPY, sdma->dma_device.cap_mask);
2256 dma_cap_set(DMA_PRIVATE, sdma->dma_device.cap_mask);
2258 INIT_LIST_HEAD(&sdma->dma_device.channels);
2261 struct sdma_channel *sdmac = &sdma->channel[i];
2263 sdmac->sdma = sdma;
2273 * that channel 0 in dmaengine counting matches sdma channel 1.
2276 vchan_init(&sdmac->vc, &sdma->dma_device);
2279 ret = sdma_init(sdma);
2283 ret = sdma_event_remap(sdma);
2287 if (sdma->drvdata->script_addrs)
2288 sdma_add_scripts(sdma, sdma->drvdata->script_addrs);
2290 sdma->dma_device.dev = &pdev->dev;
2292 sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
2293 sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
2294 sdma->dma_device.device_tx_status = sdma_tx_status;
2295 sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
2296 sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
2297 sdma->dma_device.device_config = sdma_config;
2298 sdma->dma_device.device_terminate_all = sdma_terminate_all;
2299 sdma->dma_device.device_synchronize = sdma_channel_synchronize;
2300 sdma->dma_device.src_addr_widths = SDMA_DMA_BUSWIDTHS;
2301 sdma->dma_device.dst_addr_widths = SDMA_DMA_BUSWIDTHS;
2302 sdma->dma_device.directions = SDMA_DMA_DIRECTIONS;
2303 sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
2304 sdma->dma_device.device_prep_dma_memcpy = sdma_prep_memcpy;
2305 sdma->dma_device.device_issue_pending = sdma_issue_pending;
2306 sdma->dma_device.copy_align = 2;
2307 dma_set_max_seg_size(sdma->dma_device.dev, SDMA_BD_MAX_CNT);
2309 platform_set_drvdata(pdev, sdma);
2311 ret = dma_async_device_register(&sdma->dma_device);
2318 ret = of_dma_controller_register(np, sdma_xlate, sdma);
2327 sdma->spba_start_addr = spba_res.start;
2328 sdma->spba_end_addr = spba_res.end;
2338 ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
2343 ret = sdma_get_firmware(sdma, fw_name);
2351 dma_async_device_unregister(&sdma->dma_device);
2353 kfree(sdma->script_addrs);
2355 clk_unprepare(sdma->clk_ahb);
2357 clk_unprepare(sdma->clk_ipg);
2363 struct sdma_engine *sdma = platform_get_drvdata(pdev);
2366 devm_free_irq(&pdev->dev, sdma->irq, sdma);
2367 dma_async_device_unregister(&sdma->dma_device);
2368 kfree(sdma->script_addrs);
2369 clk_unprepare(sdma->clk_ahb);
2370 clk_unprepare(sdma->clk_ipg);
2373 struct sdma_channel *sdmac = &sdma->channel[i];
2385 .name = "imx-sdma",
2397 MODULE_FIRMWARE("imx/sdma/sdma-imx6q.bin");
2400 MODULE_FIRMWARE("imx/sdma/sdma-imx7d.bin");