Lines Matching defs:sdmac
381 * @sdmac: sdma_channel pointer
393 struct sdma_channel *sdmac;
691 static int sdma_config_ownership(struct sdma_channel *sdmac,
694 struct sdma_engine *sdma = sdmac->sdma;
695 int channel = sdmac->channel;
794 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
796 struct sdma_engine *sdma = sdmac->sdma;
797 int channel = sdmac->channel;
806 if (sdmac->sw_done) {
814 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
816 struct sdma_engine *sdma = sdmac->sdma;
817 int channel = sdmac->channel;
831 static void sdma_start_desc(struct sdma_channel *sdmac)
833 struct virt_dma_desc *vd = vchan_next_desc(&sdmac->vc);
835 struct sdma_engine *sdma = sdmac->sdma;
836 int channel = sdmac->channel;
839 sdmac->desc = NULL;
842 sdmac->desc = desc = to_sdma_desc(&vd->tx);
848 sdma_enable_channel(sdma, sdmac->channel);
851 static void sdma_update_channel_loop(struct sdma_channel *sdmac)
855 enum dma_status old_status = sdmac->status;
861 while (sdmac->desc) {
862 struct sdma_desc *desc = sdmac->desc;
871 sdmac->status = DMA_ERROR;
891 spin_unlock(&sdmac->vc.lock);
893 spin_lock(&sdmac->vc.lock);
899 sdmac->status = old_status;
906 if (sdmac->desc && !is_sdma_channel_enabled(sdmac->sdma, sdmac->channel)) {
907 dev_warn(sdmac->sdma->dev, "restart cyclic channel %d\n", sdmac->channel);
908 sdma_enable_channel(sdmac->sdma, sdmac->channel);
914 struct sdma_channel *sdmac = (struct sdma_channel *) data;
918 sdmac->desc->chn_real_count = 0;
923 for (i = 0; i < sdmac->desc->num_bd; i++) {
924 bd = &sdmac->desc->bd[i];
928 sdmac->desc->chn_real_count += bd->mode.count;
932 sdmac->status = DMA_ERROR;
934 sdmac->status = DMA_COMPLETE;
949 struct sdma_channel *sdmac = &sdma->channel[channel];
952 spin_lock(&sdmac->vc.lock);
953 desc = sdmac->desc;
955 if (sdmac->flags & IMX_DMA_SG_LOOP) {
956 if (sdmac->peripheral_type != IMX_DMATYPE_HDMI)
957 sdma_update_channel_loop(sdmac);
961 mxc_sdma_handle_channel_normal(sdmac);
963 sdma_start_desc(sdmac);
967 spin_unlock(&sdmac->vc.lock);
977 static int sdma_get_pc(struct sdma_channel *sdmac,
980 struct sdma_engine *sdma = sdmac->sdma;
988 sdmac->pc_from_device = 0;
989 sdmac->pc_to_device = 0;
990 sdmac->device_to_device = 0;
991 sdmac->pc_to_pc = 0;
992 sdmac->is_ram_script = false;
1022 if (sdmac->sdma->drvdata->ecspi_fixed) {
1026 sdmac->is_ram_script = true;
1039 sdmac->is_ram_script = true;
1054 sdmac->is_ram_script = true;
1081 sdmac->is_ram_script = true;
1089 sdmac->pc_from_device = per_2_emi;
1090 sdmac->pc_to_device = emi_2_per;
1091 sdmac->device_to_device = per_2_per;
1092 sdmac->pc_to_pc = emi_2_emi;
1097 static int sdma_load_context(struct sdma_channel *sdmac)
1099 struct sdma_engine *sdma = sdmac->sdma;
1100 int channel = sdmac->channel;
1107 if (sdmac->direction == DMA_DEV_TO_MEM)
1108 load_address = sdmac->pc_from_device;
1109 else if (sdmac->direction == DMA_DEV_TO_DEV)
1110 load_address = sdmac->device_to_device;
1111 else if (sdmac->direction == DMA_MEM_TO_MEM)
1112 load_address = sdmac->pc_to_pc;
1114 load_address = sdmac->pc_to_device;
1120 dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level);
1121 dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
1122 dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
1123 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]);
1124 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]);
1134 if (sdmac->peripheral_type == IMX_DMATYPE_HDMI) {
1135 context->gReg[4] = sdmac->per_addr;
1136 context->gReg[6] = sdmac->shp_addr;
1138 context->gReg[0] = sdmac->event_mask[1];
1139 context->gReg[1] = sdmac->event_mask[0];
1140 context->gReg[2] = sdmac->per_addr;
1141 context->gReg[6] = sdmac->shp_addr;
1142 context->gReg[7] = sdmac->watermark_level;
1164 struct sdma_channel *sdmac = to_sdma_chan(chan);
1165 struct sdma_engine *sdma = sdmac->sdma;
1166 int channel = sdmac->channel;
1169 sdmac->status = DMA_ERROR;
1175 struct sdma_channel *sdmac = container_of(work, struct sdma_channel,
1185 vchan_dma_desc_free_list(&sdmac->vc, &sdmac->terminated);
1190 struct sdma_channel *sdmac = to_sdma_chan(chan);
1193 spin_lock_irqsave(&sdmac->vc.lock, flags);
1197 if (sdmac->desc) {
1198 vchan_terminate_vdesc(&sdmac->desc->vd);
1205 vchan_get_all_descriptors(&sdmac->vc, &sdmac->terminated);
1206 sdmac->desc = NULL;
1207 schedule_work(&sdmac->terminate_worker);
1210 spin_unlock_irqrestore(&sdmac->vc.lock, flags);
1217 struct sdma_channel *sdmac = to_sdma_chan(chan);
1219 vchan_synchronize(&sdmac->vc);
1221 flush_work(&sdmac->terminate_worker);
1224 static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
1226 struct sdma_engine *sdma = sdmac->sdma;
1228 int lwml = sdmac->watermark_level & SDMA_WATERMARK_LEVEL_LWML;
1229 int hwml = (sdmac->watermark_level & SDMA_WATERMARK_LEVEL_HWML) >> 16;
1231 set_bit(sdmac->event_id0 % 32, &sdmac->event_mask[1]);
1232 set_bit(sdmac->event_id1 % 32, &sdmac->event_mask[0]);
1234 if (sdmac->event_id0 > 31)
1235 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_LWE;
1237 if (sdmac->event_id1 > 31)
1238 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_HWE;
1246 sdmac->watermark_level &= ~(SDMA_WATERMARK_LEVEL_LWML |
1248 sdmac->watermark_level |= hwml;
1249 sdmac->watermark_level |= lwml << 16;
1250 swap(sdmac->event_mask[0], sdmac->event_mask[1]);
1253 if (sdmac->per_address2 >= sdma->spba_start_addr &&
1254 sdmac->per_address2 <= sdma->spba_end_addr)
1255 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SP;
1257 if (sdmac->per_address >= sdma->spba_start_addr &&
1258 sdmac->per_address <= sdma->spba_end_addr)
1259 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP;
1261 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT;
1264 static void sdma_set_watermarklevel_for_sais(struct sdma_channel *sdmac)
1270 if (sdmac->sw_done)
1271 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SW_DONE;
1273 if (sdmac->direction == DMA_DEV_TO_MEM) {
1274 n_fifos = sdmac->n_fifos_src;
1275 stride_fifos = sdmac->stride_fifos_src;
1277 n_fifos = sdmac->n_fifos_dst;
1278 stride_fifos = sdmac->stride_fifos_dst;
1281 words_per_fifo = sdmac->words_per_fifo;
1283 sdmac->watermark_level |=
1285 sdmac->watermark_level |=
1288 sdmac->watermark_level |=
1294 struct sdma_channel *sdmac = to_sdma_chan(chan);
1299 sdmac->event_mask[0] = 0;
1300 sdmac->event_mask[1] = 0;
1301 sdmac->shp_addr = 0;
1302 sdmac->per_addr = 0;
1304 switch (sdmac->peripheral_type) {
1306 sdma_config_ownership(sdmac, false, true, true);
1309 sdma_config_ownership(sdmac, false, true, false);
1312 sdma_config_ownership(sdmac, true, true, false);
1316 ret = sdma_get_pc(sdmac, sdmac->peripheral_type);
1320 if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
1321 (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
1323 if (sdmac->event_id1) {
1324 if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP ||
1325 sdmac->peripheral_type == IMX_DMATYPE_ASRC)
1326 sdma_set_watermarklevel_for_p2p(sdmac);
1328 if (sdmac->peripheral_type ==
1330 sdma_set_watermarklevel_for_sais(sdmac);
1332 __set_bit(sdmac->event_id0, sdmac->event_mask);
1336 sdmac->shp_addr = sdmac->per_address;
1337 sdmac->per_addr = sdmac->per_address2;
1339 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
1345 static int sdma_set_channel_priority(struct sdma_channel *sdmac,
1348 struct sdma_engine *sdma = sdmac->sdma;
1349 int channel = sdmac->channel;
1388 desc->bd = dma_alloc_coherent(desc->sdmac->sdma->dev, bd_size,
1402 dma_free_coherent(desc->sdmac->sdma->dev, bd_size, desc->bd,
1416 struct sdma_channel *sdmac = to_sdma_chan(chan);
1431 dev_dbg(sdmac->sdma->dev, "MEMCPY in case?\n");
1438 ret = sdma_get_pc(sdmac, IMX_DMATYPE_MEMORY);
1456 sdmac->peripheral_type = data->peripheral_type;
1457 sdmac->event_id0 = data->dma_request;
1458 sdmac->event_id1 = data->dma_request2;
1460 ret = clk_enable(sdmac->sdma->clk_ipg);
1463 ret = clk_enable(sdmac->sdma->clk_ahb);
1467 ret = sdma_set_channel_priority(sdmac, prio);
1474 clk_disable(sdmac->sdma->clk_ahb);
1476 clk_disable(sdmac->sdma->clk_ipg);
1482 struct sdma_channel *sdmac = to_sdma_chan(chan);
1483 struct sdma_engine *sdma = sdmac->sdma;
1489 sdma_event_disable(sdmac, sdmac->event_id0);
1490 if (sdmac->event_id1)
1491 sdma_event_disable(sdmac, sdmac->event_id1);
1493 sdmac->event_id0 = 0;
1494 sdmac->event_id1 = 0;
1496 sdma_set_channel_priority(sdmac, 0);
1502 static struct sdma_desc *sdma_transfer_init(struct sdma_channel *sdmac,
1507 if (!sdmac->sdma->fw_loaded && sdmac->is_ram_script) {
1508 dev_warn_once(sdmac->sdma->dev, "sdma firmware not ready!\n");
1516 sdmac->status = DMA_IN_PROGRESS;
1517 sdmac->direction = direction;
1518 sdmac->flags = 0;
1524 desc->sdmac = sdmac;
1532 sdma_config_ownership(sdmac, false, true, false);
1534 if (sdma_load_context(sdmac))
1551 struct sdma_channel *sdmac = to_sdma_chan(chan);
1552 struct sdma_engine *sdma = sdmac->sdma;
1553 int channel = sdmac->channel;
1565 desc = sdma_transfer_init(sdmac, DMA_MEM_TO_MEM,
1600 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
1608 struct sdma_channel *sdmac = to_sdma_chan(chan);
1609 struct sdma_engine *sdma = sdmac->sdma;
1611 int channel = sdmac->channel;
1615 sdma_config_write(chan, &sdmac->slave_config, direction);
1617 desc = sdma_transfer_init(sdmac, direction, sg_len);
1641 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1644 switch (sdmac->word_size) {
1678 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
1683 sdmac->status = DMA_ERROR;
1692 struct sdma_channel *sdmac = to_sdma_chan(chan);
1693 struct sdma_engine *sdma = sdmac->sdma;
1695 int channel = sdmac->channel;
1701 if (sdmac->peripheral_type != IMX_DMATYPE_HDMI)
1704 sdma_config_write(chan, &sdmac->slave_config, direction);
1706 desc = sdma_transfer_init(sdmac, direction, num_periods);
1712 sdmac->flags |= IMX_DMA_SG_LOOP;
1720 if (sdmac->peripheral_type == IMX_DMATYPE_HDMI)
1721 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
1731 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1733 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1736 bd->mode.command = sdmac->word_size;
1755 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
1760 sdmac->status = DMA_ERROR;
1768 struct sdma_channel *sdmac = to_sdma_chan(chan);
1771 sdmac->per_address = dmaengine_cfg->src_addr;
1772 sdmac->watermark_level = dmaengine_cfg->src_maxburst *
1774 sdmac->word_size = dmaengine_cfg->src_addr_width;
1776 sdmac->per_address2 = dmaengine_cfg->src_addr;
1777 sdmac->per_address = dmaengine_cfg->dst_addr;
1778 sdmac->watermark_level = dmaengine_cfg->src_maxburst &
1780 sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) &
1782 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1783 } else if (sdmac->peripheral_type == IMX_DMATYPE_HDMI) {
1784 sdmac->per_address = dmaengine_cfg->dst_addr;
1785 sdmac->per_address2 = dmaengine_cfg->src_addr;
1786 sdmac->watermark_level = 0;
1788 sdmac->per_address = dmaengine_cfg->dst_addr;
1789 sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
1791 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1793 sdmac->direction = direction;
1800 struct sdma_channel *sdmac = to_sdma_chan(chan);
1801 struct sdma_engine *sdma = sdmac->sdma;
1803 memcpy(&sdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg));
1813 sdmac->n_fifos_src = sdmacfg->n_fifos_src;
1814 sdmac->n_fifos_dst = sdmacfg->n_fifos_dst;
1815 sdmac->stride_fifos_src = sdmacfg->stride_fifos_src;
1816 sdmac->stride_fifos_dst = sdmacfg->stride_fifos_dst;
1817 sdmac->words_per_fifo = sdmacfg->words_per_fifo;
1818 sdmac->sw_done = sdmacfg->sw_done;
1822 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
1824 sdma_event_enable(sdmac, sdmac->event_id0);
1826 if (sdmac->event_id1) {
1827 if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events)
1829 sdma_event_enable(sdmac, sdmac->event_id1);
1839 struct sdma_channel *sdmac = to_sdma_chan(chan);
1850 spin_lock_irqsave(&sdmac->vc.lock, flags);
1852 vd = vchan_find_desc(&sdmac->vc, cookie);
1855 else if (sdmac->desc && sdmac->desc->vd.tx.cookie == cookie)
1856 desc = sdmac->desc;
1859 if (sdmac->flags & IMX_DMA_SG_LOOP)
1868 spin_unlock_irqrestore(&sdmac->vc.lock, flags);
1873 return sdmac->status;
1878 struct sdma_channel *sdmac = to_sdma_chan(chan);
1881 spin_lock_irqsave(&sdmac->vc.lock, flags);
1882 if (vchan_issue_pending(&sdmac->vc) && !sdmac->desc)
1883 sdma_start_desc(sdmac);
1884 spin_unlock_irqrestore(&sdmac->vc.lock, flags);
2148 struct sdma_channel *sdmac = to_sdma_chan(chan);
2154 sdmac->data = *data;
2155 chan->private = &sdmac->data;
2178 * be set to sdmac->event_id1.
2261 struct sdma_channel *sdmac = &sdma->channel[i];
2263 sdmac->sdma = sdma;
2265 sdmac->channel = i;
2266 sdmac->vc.desc_free = sdma_desc_free;
2267 INIT_LIST_HEAD(&sdmac->terminated);
2268 INIT_WORK(&sdmac->terminate_worker,
2276 vchan_init(&sdmac->vc, &sdma->dma_device);
2373 struct sdma_channel *sdmac = &sdma->channel[i];
2375 tasklet_kill(&sdmac->vc.task);
2376 sdma_free_chan_resources(&sdmac->vc.chan);