Lines Matching refs:imxdmac
222 static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
226 if (!list_empty(&imxdmac->ld_active)) {
227 desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc,
248 static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
250 struct imxdma_engine *imxdma = imxdmac->imxdma;
253 return imxdmac->hw_chaining;
263 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
264 struct imxdma_engine *imxdma = imxdmac->imxdma;
274 DMA_DAR(imxdmac->channel));
277 DMA_SAR(imxdmac->channel));
279 imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel));
282 "size 0x%08x\n", __func__, imxdmac->channel,
283 imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)),
284 imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)),
285 imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel)));
290 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
291 struct imxdma_engine *imxdma = imxdmac->imxdma;
292 int channel = imxdmac->channel;
306 d->sg && imxdma_hw_chain(imxdmac)) {
320 static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
322 struct imxdma_engine *imxdma = imxdmac->imxdma;
323 int channel = imxdmac->channel;
328 if (imxdma_hw_chain(imxdmac))
329 del_timer(&imxdmac->watchdog);
342 struct imxdma_channel *imxdmac = from_timer(imxdmac, t, watchdog);
343 struct imxdma_engine *imxdma = imxdmac->imxdma;
344 int channel = imxdmac->channel;
349 tasklet_schedule(&imxdmac->dma_tasklet);
351 imxdmac->channel);
407 static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
409 struct imxdma_engine *imxdma = imxdmac->imxdma;
410 int chno = imxdmac->channel;
415 if (list_empty(&imxdmac->ld_active)) {
420 desc = list_first_entry(&imxdmac->ld_active,
434 if (imxdma_hw_chain(imxdmac)) {
438 mod_timer(&imxdmac->watchdog,
451 if (imxdma_chan_is_doing_cyclic(imxdmac))
453 tasklet_schedule(&imxdmac->dma_tasklet);
458 if (imxdma_hw_chain(imxdmac)) {
459 del_timer(&imxdmac->watchdog);
467 tasklet_schedule(&imxdmac->dma_tasklet);
493 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
494 struct imxdma_engine *imxdma = imxdmac->imxdma;
519 imxdmac->slot_2d = slot;
520 imxdmac->enabled_2d = true;
541 imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel));
542 imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel));
544 DMA_CCR(imxdmac->channel));
546 imx_dmav1_writel(imxdma, d->len, DMA_CNTR(imxdmac->channel));
550 __func__, imxdmac->channel,
559 imx_dmav1_writel(imxdma, imxdmac->per_address,
560 DMA_SAR(imxdmac->channel));
561 imx_dmav1_writel(imxdma, imxdmac->ccr_from_device,
562 DMA_CCR(imxdmac->channel));
566 __func__, imxdmac->channel,
568 (unsigned long long)imxdmac->per_address);
570 imx_dmav1_writel(imxdma, imxdmac->per_address,
571 DMA_DAR(imxdmac->channel));
572 imx_dmav1_writel(imxdma, imxdmac->ccr_to_device,
573 DMA_CCR(imxdmac->channel));
577 __func__, imxdmac->channel,
579 (unsigned long long)imxdmac->per_address);
582 __func__, imxdmac->channel);
598 struct imxdma_channel *imxdmac = from_tasklet(imxdmac, t, dma_tasklet);
599 struct imxdma_engine *imxdma = imxdmac->imxdma;
605 if (list_empty(&imxdmac->ld_active)) {
610 desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node);
616 if (imxdma_chan_is_doing_cyclic(imxdmac))
622 if (imxdmac->enabled_2d) {
623 imxdma->slots_2d[imxdmac->slot_2d].count--;
624 imxdmac->enabled_2d = false;
627 list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free);
629 if (!list_empty(&imxdmac->ld_queue)) {
630 next_desc = list_first_entry(&imxdmac->ld_queue,
632 list_move_tail(imxdmac->ld_queue.next, &imxdmac->ld_active);
635 __func__, imxdmac->channel);
645 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
646 struct imxdma_engine *imxdma = imxdmac->imxdma;
649 imxdma_disable_hw(imxdmac);
652 list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
653 list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
662 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
663 struct imxdma_engine *imxdma = imxdmac->imxdma;
667 imxdmac->per_address = dmaengine_cfg->src_addr;
668 imxdmac->watermark_level = dmaengine_cfg->src_maxburst;
669 imxdmac->word_size = dmaengine_cfg->src_addr_width;
671 imxdmac->per_address = dmaengine_cfg->dst_addr;
672 imxdmac->watermark_level = dmaengine_cfg->dst_maxburst;
673 imxdmac->word_size = dmaengine_cfg->dst_addr_width;
676 switch (imxdmac->word_size) {
689 imxdmac->hw_chaining = 0;
691 imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) |
694 imxdmac->ccr_to_device =
697 imx_dmav1_writel(imxdma, imxdmac->dma_request,
698 DMA_RSSR(imxdmac->channel));
701 imx_dmav1_writel(imxdma, imxdmac->watermark_level *
702 imxdmac->word_size, DMA_BLR(imxdmac->channel));
710 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
712 memcpy(&imxdmac->config, dmaengine_cfg, sizeof(*dmaengine_cfg));
726 struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan);
727 struct imxdma_engine *imxdma = imxdmac->imxdma;
732 list_move_tail(imxdmac->ld_free.next, &imxdmac->ld_queue);
741 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
745 imxdmac->dma_request = data->dma_request;
747 while (imxdmac->descs_allocated < IMXDMA_MAX_CHAN_DESCRIPTORS) {
759 list_add_tail(&desc->node, &imxdmac->ld_free);
760 imxdmac->descs_allocated++;
763 if (!imxdmac->descs_allocated)
766 return imxdmac->descs_allocated;
771 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
772 struct imxdma_engine *imxdma = imxdmac->imxdma;
778 imxdma_disable_hw(imxdmac);
779 list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
780 list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
784 list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) {
786 imxdmac->descs_allocated--;
788 INIT_LIST_HEAD(&imxdmac->ld_free);
790 kfree(imxdmac->sg_list);
791 imxdmac->sg_list = NULL;
799 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
804 if (list_empty(&imxdmac->ld_free) ||
805 imxdma_chan_is_doing_cyclic(imxdmac))
808 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
814 imxdma_config_write(chan, &imxdmac->config, direction);
816 switch (imxdmac->word_size) {
837 desc->src = imxdmac->per_address;
839 desc->dest = imxdmac->per_address;
852 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
853 struct imxdma_engine *imxdma = imxdmac->imxdma;
859 __func__, imxdmac->channel, buf_len, period_len);
861 if (list_empty(&imxdmac->ld_free) ||
862 imxdma_chan_is_doing_cyclic(imxdmac))
865 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
867 kfree(imxdmac->sg_list);
869 imxdmac->sg_list = kcalloc(periods + 1,
871 if (!imxdmac->sg_list)
874 sg_init_table(imxdmac->sg_list, periods);
877 sg_assign_page(&imxdmac->sg_list[i], NULL);
878 imxdmac->sg_list[i].offset = 0;
879 imxdmac->sg_list[i].dma_address = dma_addr;
880 sg_dma_len(&imxdmac->sg_list[i]) = period_len;
885 sg_chain(imxdmac->sg_list, periods + 1, imxdmac->sg_list);
888 desc->sg = imxdmac->sg_list;
893 desc->src = imxdmac->per_address;
895 desc->dest = imxdmac->per_address;
900 imxdma_config_write(chan, &imxdmac->config, direction);
909 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
910 struct imxdma_engine *imxdma = imxdmac->imxdma;
914 __func__, imxdmac->channel, (unsigned long long)src,
917 if (list_empty(&imxdmac->ld_free) ||
918 imxdma_chan_is_doing_cyclic(imxdmac))
921 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
940 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
941 struct imxdma_engine *imxdma = imxdmac->imxdma;
946 imxdmac->channel, (unsigned long long)xt->src_start,
951 if (list_empty(&imxdmac->ld_free) ||
952 imxdma_chan_is_doing_cyclic(imxdmac))
958 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
982 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
983 struct imxdma_engine *imxdma = imxdmac->imxdma;
988 if (list_empty(&imxdmac->ld_active) &&
989 !list_empty(&imxdmac->ld_queue)) {
990 desc = list_first_entry(&imxdmac->ld_queue,
996 __func__, imxdmac->channel);
998 list_move_tail(imxdmac->ld_queue.next,
999 &imxdmac->ld_active);
1124 struct imxdma_channel *imxdmac = &imxdma->channel[i];
1136 imxdmac->irq = irq + i;
1137 timer_setup(&imxdmac->watchdog, imxdma_watchdog, 0);
1140 imxdmac->imxdma = imxdma;
1142 INIT_LIST_HEAD(&imxdmac->ld_queue);
1143 INIT_LIST_HEAD(&imxdmac->ld_free);
1144 INIT_LIST_HEAD(&imxdmac->ld_active);
1146 tasklet_setup(&imxdmac->dma_tasklet, imxdma_tasklet);
1147 imxdmac->chan.device = &imxdma->dma_device;
1148 dma_cookie_init(&imxdmac->chan);
1149 imxdmac->channel = i;
1152 list_add_tail(&imxdmac->chan.device_node,
1210 struct imxdma_channel *imxdmac = &imxdma->channel[i];
1213 disable_irq(imxdmac->irq);
1215 tasklet_kill(&imxdmac->dma_tasklet);