Lines Matching refs:dev
78 struct device *dev = &pdev->dev;
85 dev_err(dev, "Not MSI-X interrupt capable.\n");
92 dev_err(dev, "Failed enabling %d MSIX entries: %d\n", msixcnt, rc);
95 dev_dbg(dev, "Enabled %d msix vectors\n", msixcnt);
102 dev_err(dev, "Failed to allocate misc interrupt.\n");
105 dev_dbg(dev, "Requested idxd-misc handler on msix vector %d\n", ie->vector);
126 dev_err(dev, "No usable interrupts\n");
148 struct device *dev = &idxd->pdev->dev;
154 GFP_KERNEL, dev_to_node(dev));
158 idxd->wq_enable_map = bitmap_zalloc_node(idxd->max_wqs, GFP_KERNEL, dev_to_node(dev));
165 wq = kzalloc_node(sizeof(*wq), GFP_KERNEL, dev_to_node(dev));
192 wq->wqcfg = kzalloc_node(idxd->wqcfg_size, GFP_KERNEL, dev_to_node(dev));
227 struct device *dev = &idxd->pdev->dev;
232 GFP_KERNEL, dev_to_node(dev));
237 engine = kzalloc_node(sizeof(*engine), GFP_KERNEL, dev_to_node(dev));
273 struct device *dev = &idxd->pdev->dev;
279 GFP_KERNEL, dev_to_node(dev));
284 group = kzalloc_node(sizeof(*group), GFP_KERNEL, dev_to_node(dev));
344 struct device *dev = &idxd->pdev->dev;
352 evl = kzalloc_node(sizeof(*evl), GFP_KERNEL, dev_to_node(dev));
380 struct device *dev = &idxd->pdev->dev;
397 idxd->wq = create_workqueue(dev_name(dev));
427 struct device *dev = &idxd->pdev->dev;
432 dev_dbg(dev, "IDXD Group Config Offset: %#x\n", idxd->grpcfg_offset);
434 dev_dbg(dev, "IDXD Work Queue Config Offset: %#x\n", idxd->wqcfg_offset);
436 dev_dbg(dev, "IDXD MSIX Permission Offset: %#x\n", idxd->msix_perm_offset);
438 dev_dbg(dev, "IDXD Perfmon Offset: %#x\n", idxd->perfmon_offset);
456 struct device *dev = &idxd->pdev->dev;
461 dev_dbg(dev, "gen_cap: %#llx\n", idxd->hw.gen_cap.bits);
465 dev_dbg(dev, "cmd_cap: %#x\n", idxd->hw.cmd_cap);
473 dev_dbg(dev, "max xfer size: %llu bytes\n", idxd->max_xfer_bytes);
475 dev_dbg(dev, "max batch size: %u\n", idxd->max_batch_size);
482 dev_dbg(dev, "group_cap: %#llx\n", idxd->hw.group_cap.bits);
484 dev_dbg(dev, "max groups: %u\n", idxd->max_groups);
486 dev_dbg(dev, "max read buffers: %u\n", idxd->max_rdbufs);
492 dev_dbg(dev, "engine_cap: %#llx\n", idxd->hw.engine_cap.bits);
494 dev_dbg(dev, "max engines: %u\n", idxd->max_engines);
498 dev_dbg(dev, "wq_cap: %#llx\n", idxd->hw.wq_cap.bits);
500 dev_dbg(dev, "total workqueue size: %u\n", idxd->max_wq_size);
502 dev_dbg(dev, "max workqueues: %u\n", idxd->max_wqs);
504 dev_dbg(dev, "wqcfg size: %u\n", idxd->wqcfg_size);
510 dev_dbg(dev, "opcap[%d]: %#llx\n", i, idxd->hw.opcap.bits[i]);
521 struct device *dev = &pdev->dev;
526 idxd = kzalloc_node(sizeof(*idxd), GFP_KERNEL, dev_to_node(dev));
538 idxd->opcap_bmap = bitmap_zalloc_node(IDXD_MAX_OPCAP_BITS, GFP_KERNEL, dev_to_node(dev));
545 conf_dev->parent = dev;
563 struct device *dev = &pdev->dev;
572 domain = iommu_get_domain_for_dev(dev);
576 pasid = iommu_alloc_global_pasid(dev);
584 ret = iommu_attach_device_pasid(domain, dev, pasid);
586 dev_err(dev, "failed to attach device pasid %d, domain type %d",
602 struct device *dev = &pdev->dev;
605 domain = iommu_get_domain_for_dev(dev);
609 iommu_detach_device_pasid(domain, dev, idxd->pasid);
621 ret = iommu_dev_enable_feature(&pdev->dev, IOMMU_DEV_FEAT_IOPF);
625 ret = iommu_dev_enable_feature(&pdev->dev, IOMMU_DEV_FEAT_SVA);
627 iommu_dev_disable_feature(&pdev->dev, IOMMU_DEV_FEAT_IOPF);
634 iommu_dev_disable_feature(&pdev->dev, IOMMU_DEV_FEAT_SVA);
635 iommu_dev_disable_feature(&pdev->dev, IOMMU_DEV_FEAT_IOPF);
641 struct device *dev = &pdev->dev;
644 dev_dbg(dev, "%s entered and resetting device\n", __func__);
649 dev_dbg(dev, "IDXD reset complete\n");
653 dev_warn(dev, "Unable to turn on user SVA feature.\n");
659 dev_warn(dev, "No in-kernel DMA with PASID. %d\n", rc);
664 dev_warn(dev, "User forced SVA off via module param.\n");
676 dev_dbg(dev, "Loading RO device config\n");
690 dev_warn(dev, "Failed to initialize perfmon. No PMU support: %d\n", rc);
692 dev_dbg(dev, "IDXD device %d probed successfully\n", idxd->id);
718 struct device *dev = &pdev->dev;
727 dev_dbg(dev, "Alloc IDXD context\n");
734 dev_dbg(dev, "Mapping BARs\n");
741 dev_dbg(dev, "Set DMA masks\n");
742 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
746 dev_dbg(dev, "Set PCI master\n");
753 dev_err(dev, "Intel(R) IDXD DMA Engine init failed\n");
759 dev_err(dev, "IDXD sysfs setup failed\n");
765 dev_warn(dev, "IDXD debugfs failed to setup\n");
767 dev_info(&pdev->dev, "Intel(R) Accelerator Device (v%x)\n",
803 dev_err(&pdev->dev, "Disabling device failed\n");