Lines Matching defs:hsu
34 #include "hsu.h"
159 if (nr >= chip->hsu->nr_channels)
162 hsuc = &chip->hsu->chan[nr];
218 if (nr >= chip->hsu->nr_channels)
221 hsuc = &chip->hsu->chan[nr];
429 struct hsu_dma *hsu;
434 hsu = devm_kzalloc(chip->dev, sizeof(*hsu), GFP_KERNEL);
435 if (!hsu)
438 chip->hsu = hsu;
441 hsu->nr_channels = (chip->length - chip->offset) / HSU_DMA_CHAN_LENGTH;
443 hsu->chan = devm_kcalloc(chip->dev, hsu->nr_channels,
444 sizeof(*hsu->chan), GFP_KERNEL);
445 if (!hsu->chan)
448 INIT_LIST_HEAD(&hsu->dma.channels);
449 for (i = 0; i < hsu->nr_channels; i++) {
450 struct hsu_dma_chan *hsuc = &hsu->chan[i];
453 vchan_init(&hsuc->vchan, &hsu->dma);
459 dma_cap_set(DMA_SLAVE, hsu->dma.cap_mask);
460 dma_cap_set(DMA_PRIVATE, hsu->dma.cap_mask);
462 hsu->dma.device_free_chan_resources = hsu_dma_free_chan_resources;
464 hsu->dma.device_prep_slave_sg = hsu_dma_prep_slave_sg;
466 hsu->dma.device_issue_pending = hsu_dma_issue_pending;
467 hsu->dma.device_tx_status = hsu_dma_tx_status;
469 hsu->dma.device_config = hsu_dma_slave_config;
470 hsu->dma.device_pause = hsu_dma_pause;
471 hsu->dma.device_resume = hsu_dma_resume;
472 hsu->dma.device_terminate_all = hsu_dma_terminate_all;
473 hsu->dma.device_synchronize = hsu_dma_synchronize;
475 hsu->dma.src_addr_widths = HSU_DMA_BUSWIDTHS;
476 hsu->dma.dst_addr_widths = HSU_DMA_BUSWIDTHS;
477 hsu->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
478 hsu->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
480 hsu->dma.dev = chip->dev;
482 dma_set_max_seg_size(hsu->dma.dev, HSU_CH_DxTSR_MASK);
484 ret = dma_async_device_register(&hsu->dma);
488 dev_info(chip->dev, "Found HSU DMA, %d channels\n", hsu->nr_channels);
495 struct hsu_dma *hsu = chip->hsu;
498 dma_async_device_unregister(&hsu->dma);
500 for (i = 0; i < hsu->nr_channels; i++) {
501 struct hsu_dma_chan *hsuc = &hsu->chan[i];