Lines Matching refs:chan
39 #define chan_dbg(chan, fmt, arg...) \
40 dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg)
41 #define chan_err(chan, fmt, arg...) \
42 dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
50 static void set_sr(struct fsldma_chan *chan, u32 val)
52 FSL_DMA_OUT(chan, &chan->regs->sr, val, 32);
55 static u32 get_sr(struct fsldma_chan *chan)
57 return FSL_DMA_IN(chan, &chan->regs->sr, 32);
60 static void set_mr(struct fsldma_chan *chan, u32 val)
62 FSL_DMA_OUT(chan, &chan->regs->mr, val, 32);
65 static u32 get_mr(struct fsldma_chan *chan)
67 return FSL_DMA_IN(chan, &chan->regs->mr, 32);
70 static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr)
72 FSL_DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64);
75 static dma_addr_t get_cdar(struct fsldma_chan *chan)
77 return FSL_DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN;
80 static void set_bcr(struct fsldma_chan *chan, u32 val)
82 FSL_DMA_OUT(chan, &chan->regs->bcr, val, 32);
85 static u32 get_bcr(struct fsldma_chan *chan)
87 return FSL_DMA_IN(chan, &chan->regs->bcr, 32);
94 static void set_desc_cnt(struct fsldma_chan *chan,
97 hw->count = CPU_TO_DMA(chan, count, 32);
100 static void set_desc_src(struct fsldma_chan *chan,
105 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
107 hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64);
110 static void set_desc_dst(struct fsldma_chan *chan,
115 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
117 hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64);
120 static void set_desc_next(struct fsldma_chan *chan,
125 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
127 hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64);
130 static void set_ld_eol(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
134 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
137 desc->hw.next_ln_addr = CPU_TO_DMA(chan,
138 DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL
146 static void dma_init(struct fsldma_chan *chan)
149 set_mr(chan, 0);
151 switch (chan->feature & FSL_DMA_IP_MASK) {
158 set_mr(chan, FSL_DMA_MR_BWC | FSL_DMA_MR_EIE
166 set_mr(chan, FSL_DMA_MR_EOTIE | FSL_DMA_MR_PRC_RM);
171 static int dma_is_idle(struct fsldma_chan *chan)
173 u32 sr = get_sr(chan);
184 static void dma_start(struct fsldma_chan *chan)
188 mode = get_mr(chan);
190 if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) {
191 set_bcr(chan, 0);
197 if (chan->feature & FSL_DMA_CHAN_START_EXT) {
204 set_mr(chan, mode);
207 static void dma_halt(struct fsldma_chan *chan)
213 mode = get_mr(chan);
220 if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
222 set_mr(chan, mode);
229 set_mr(chan, mode);
233 if (dma_is_idle(chan))
239 if (!dma_is_idle(chan))
240 chan_err(chan, "DMA halt timeout!\n");
245 * @chan : Freescale DMA channel
254 static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size)
258 mode = get_mr(chan);
273 set_mr(chan, mode);
278 * @chan : Freescale DMA channel
287 static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size)
291 mode = get_mr(chan);
306 set_mr(chan, mode);
311 * @chan : Freescale DMA channel
321 static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size)
327 mode = get_mr(chan);
331 set_mr(chan, mode);
336 * @chan : Freescale DMA channel
343 static void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable)
346 chan->feature |= FSL_DMA_CHAN_PAUSE_EXT;
348 chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT;
353 * @chan : Freescale DMA channel
361 static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable)
364 chan->feature |= FSL_DMA_CHAN_START_EXT;
366 chan->feature &= ~FSL_DMA_CHAN_START_EXT;
371 struct fsldma_chan *chan;
376 chan = to_fsl_chan(dchan);
378 fsl_chan_toggle_ext_start(chan, enable);
383 static void append_ld_queue(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
385 struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev);
387 if (list_empty(&chan->ld_pending))
397 set_desc_next(chan, &tail->hw, desc->async_tx.phys);
404 list_splice_tail_init(&desc->tx_list, &chan->ld_pending);
409 struct fsldma_chan *chan = to_fsl_chan(tx->chan);
414 spin_lock_bh(&chan->desc_lock);
417 if (unlikely(chan->pm_state != RUNNING)) {
418 chan_dbg(chan, "cannot submit due to suspend\n");
419 spin_unlock_bh(&chan->desc_lock);
433 append_ld_queue(chan, desc);
435 spin_unlock_bh(&chan->desc_lock);
442 * @chan : Freescale DMA channel
445 static void fsl_dma_free_descriptor(struct fsldma_chan *chan,
449 chan_dbg(chan, "LD %p free\n", desc);
450 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
455 * @chan : Freescale DMA channel
459 static struct fsl_desc_sw *fsl_dma_alloc_descriptor(struct fsldma_chan *chan)
464 desc = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &pdesc);
466 chan_dbg(chan, "out of memory for link descriptor\n");
471 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
475 chan_dbg(chan, "LD %p allocated\n", desc);
483 * @chan: Freescale DMA channel
488 static void fsldma_clean_completed_descriptor(struct fsldma_chan *chan)
493 list_for_each_entry_safe(desc, _desc, &chan->ld_completed, node)
495 fsl_dma_free_descriptor(chan, desc);
500 * @chan: Freescale DMA channel
507 static dma_cookie_t fsldma_run_tx_complete_actions(struct fsldma_chan *chan,
532 * @chan: Freescale DMA channel
538 static void fsldma_clean_running_descriptor(struct fsldma_chan *chan,
553 list_add_tail(&desc->node, &chan->ld_completed);
557 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
562 * @chan : Freescale DMA channel
565 * LOCKING: must hold chan->desc_lock
567 static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan)
575 if (list_empty(&chan->ld_pending)) {
576 chan_dbg(chan, "no pending LDs\n");
585 if (!chan->idle) {
586 chan_dbg(chan, "DMA controller still busy\n");
599 chan_dbg(chan, "idle, starting controller\n");
600 desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node);
601 list_splice_tail_init(&chan->ld_pending, &chan->ld_running);
608 if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
611 mode = get_mr(chan);
613 set_mr(chan, mode);
620 set_cdar(chan, desc->async_tx.phys);
621 get_cdar(chan);
623 dma_start(chan);
624 chan->idle = false;
630 * @chan: Freescale DMA channel
636 static void fsldma_cleanup_descriptors(struct fsldma_chan *chan)
640 dma_addr_t curr_phys = get_cdar(chan);
643 fsldma_clean_completed_descriptor(chan);
646 list_for_each_entry_safe(desc, _desc, &chan->ld_running, node) {
661 if (!dma_is_idle(chan))
665 cookie = fsldma_run_tx_complete_actions(chan, desc, cookie);
667 fsldma_clean_running_descriptor(chan, desc);
676 fsl_chan_xfer_ld_queue(chan);
679 chan->common.completed_cookie = cookie;
684 * @chan : Freescale DMA channel
692 struct fsldma_chan *chan = to_fsl_chan(dchan);
695 if (chan->desc_pool)
702 chan->desc_pool = dma_pool_create(chan->name, chan->dev,
705 if (!chan->desc_pool) {
706 chan_err(chan, "unable to allocate descriptor pool\n");
716 * @chan: Freescae DMA channel
719 * LOCKING: must hold chan->desc_lock
721 static void fsldma_free_desc_list(struct fsldma_chan *chan,
727 fsl_dma_free_descriptor(chan, desc);
730 static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan,
736 fsl_dma_free_descriptor(chan, desc);
741 * @chan : Freescale DMA channel
745 struct fsldma_chan *chan = to_fsl_chan(dchan);
747 chan_dbg(chan, "free all channel resources\n");
748 spin_lock_bh(&chan->desc_lock);
749 fsldma_cleanup_descriptors(chan);
750 fsldma_free_desc_list(chan, &chan->ld_pending);
751 fsldma_free_desc_list(chan, &chan->ld_running);
752 fsldma_free_desc_list(chan, &chan->ld_completed);
753 spin_unlock_bh(&chan->desc_lock);
755 dma_pool_destroy(chan->desc_pool);
756 chan->desc_pool = NULL;
764 struct fsldma_chan *chan;
774 chan = to_fsl_chan(dchan);
779 new = fsl_dma_alloc_descriptor(chan);
781 chan_err(chan, "%s\n", msg_ld_oom);
787 set_desc_cnt(chan, &new->hw, copy);
788 set_desc_src(chan, &new->hw, dma_src);
789 set_desc_dst(chan, &new->hw, dma_dst);
794 set_desc_next(chan, &prev->hw, new->async_tx.phys);
812 set_ld_eol(chan, new);
820 fsldma_free_desc_list_reverse(chan, &first->tx_list);
826 struct fsldma_chan *chan;
831 chan = to_fsl_chan(dchan);
833 spin_lock_bh(&chan->desc_lock);
836 dma_halt(chan);
839 fsldma_free_desc_list(chan, &chan->ld_pending);
840 fsldma_free_desc_list(chan, &chan->ld_running);
841 fsldma_free_desc_list(chan, &chan->ld_completed);
842 chan->idle = true;
844 spin_unlock_bh(&chan->desc_lock);
851 struct fsldma_chan *chan;
857 chan = to_fsl_chan(dchan);
860 if (!chan->set_request_count)
869 chan->set_request_count(chan, size);
876 * @chan : Freescale DMA channel
880 struct fsldma_chan *chan = to_fsl_chan(dchan);
882 spin_lock_bh(&chan->desc_lock);
883 fsl_chan_xfer_ld_queue(chan);
884 spin_unlock_bh(&chan->desc_lock);
889 * @chan : Freescale DMA channel
895 struct fsldma_chan *chan = to_fsl_chan(dchan);
902 spin_lock_bh(&chan->desc_lock);
903 fsldma_cleanup_descriptors(chan);
904 spin_unlock_bh(&chan->desc_lock);
915 struct fsldma_chan *chan = data;
919 stat = get_sr(chan);
920 set_sr(chan, stat);
921 chan_dbg(chan, "irq: stat = 0x%x\n", stat);
929 chan_err(chan, "Transfer Error!\n");
937 chan_dbg(chan, "irq: Programming Error INT\n");
939 if (get_bcr(chan) != 0)
940 chan_err(chan, "Programming Error!\n");
948 chan_dbg(chan, "irq: End-of-Chain link INT\n");
958 chan_dbg(chan, "irq: End-of-link INT\n");
963 if (!dma_is_idle(chan))
964 chan_err(chan, "irq: controller not idle!\n");
968 chan_err(chan, "irq: unhandled sr 0x%08x\n", stat);
975 tasklet_schedule(&chan->tasklet);
976 chan_dbg(chan, "irq: Exit\n");
982 struct fsldma_chan *chan = from_tasklet(chan, t, tasklet);
984 chan_dbg(chan, "tasklet entry\n");
986 spin_lock(&chan->desc_lock);
989 chan->idle = true;
992 fsldma_cleanup_descriptors(chan);
994 spin_unlock(&chan->desc_lock);
996 chan_dbg(chan, "tasklet exit\n");
1002 struct fsldma_chan *chan;
1013 chan = fdev->chan[i];
1014 if (!chan)
1018 dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id);
1019 fsldma_chan_irq(irq, chan);
1032 struct fsldma_chan *chan;
1042 chan = fdev->chan[i];
1043 if (chan && chan->irq) {
1044 chan_dbg(chan, "free per-channel IRQ\n");
1045 free_irq(chan->irq, chan);
1052 struct fsldma_chan *chan;
1066 chan = fdev->chan[i];
1067 if (!chan)
1070 if (!chan->irq) {
1071 chan_err(chan, "interrupts property missing in device tree\n");
1076 chan_dbg(chan, "request per-channel IRQ\n");
1077 ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED,
1078 "fsldma-chan", chan);
1080 chan_err(chan, "unable to request per-channel IRQ\n");
1089 chan = fdev->chan[i];
1090 if (!chan)
1093 if (!chan->irq)
1096 free_irq(chan->irq, chan);
1109 struct fsldma_chan *chan;
1114 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
1115 if (!chan) {
1121 chan->regs = of_iomap(node, 0);
1122 if (!chan->regs) {
1134 chan->feature = feature;
1136 fdev->feature = chan->feature;
1142 WARN_ON(fdev->feature != chan->feature);
1144 chan->dev = fdev->dev;
1145 chan->id = (res.start & 0xfff) < 0x300 ?
1148 if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) {
1154 fdev->chan[chan->id] = chan;
1155 tasklet_setup(&chan->tasklet, dma_do_tasklet);
1156 snprintf(chan->name, sizeof(chan->name), "chan%d", chan->id);
1159 dma_init(chan);
1162 set_cdar(chan, 0);
1164 switch (chan->feature & FSL_DMA_IP_MASK) {
1166 chan->toggle_ext_pause = fsl_chan_toggle_ext_pause;
1169 chan->toggle_ext_start = fsl_chan_toggle_ext_start;
1170 chan->set_src_loop_size = fsl_chan_set_src_loop_size;
1171 chan->set_dst_loop_size = fsl_chan_set_dst_loop_size;
1172 chan->set_request_count = fsl_chan_set_request_count;
1175 spin_lock_init(&chan->desc_lock);
1176 INIT_LIST_HEAD(&chan->ld_pending);
1177 INIT_LIST_HEAD(&chan->ld_running);
1178 INIT_LIST_HEAD(&chan->ld_completed);
1179 chan->idle = true;
1181 chan->pm_state = RUNNING;
1184 chan->common.device = &fdev->common;
1185 dma_cookie_init(&chan->common);
1188 chan->irq = irq_of_parse_and_map(node, 0);
1191 list_add_tail(&chan->common.device_node, &fdev->common.channels);
1193 dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible,
1194 chan->irq ? chan->irq : fdev->irq);
1199 iounmap(chan->regs);
1201 kfree(chan);
1206 static void fsl_dma_chan_remove(struct fsldma_chan *chan)
1208 irq_dispose_mapping(chan->irq);
1209 list_del(&chan->common.device_node);
1210 iounmap(chan->regs);
1211 kfree(chan);
1298 if (fdev->chan[i])
1299 fsl_dma_chan_remove(fdev->chan[i]);
1320 if (fdev->chan[i])
1321 fsl_dma_chan_remove(fdev->chan[i]);
1335 struct fsldma_chan *chan;
1339 chan = fdev->chan[i];
1340 if (!chan)
1343 spin_lock_bh(&chan->desc_lock);
1344 if (unlikely(!chan->idle))
1346 chan->regs_save.mr = get_mr(chan);
1347 chan->pm_state = SUSPENDED;
1348 spin_unlock_bh(&chan->desc_lock);
1354 chan = fdev->chan[i];
1355 if (!chan)
1357 chan->pm_state = RUNNING;
1358 spin_unlock_bh(&chan->desc_lock);
1366 struct fsldma_chan *chan;
1371 chan = fdev->chan[i];
1372 if (!chan)
1375 spin_lock_bh(&chan->desc_lock);
1376 mode = chan->regs_save.mr
1378 set_mr(chan, mode);
1379 chan->pm_state = RUNNING;
1380 spin_unlock_bh(&chan->desc_lock);