Lines Matching refs:fsl_qdma
309 struct fsl_qdma_engine *fsl_qdma = fsl_chan->qdma;
350 fsl_qdma->desc_allocated--;
485 struct fsl_qdma_engine *fsl_qdma)
492 queue_num = fsl_qdma->n_queues;
493 block_number = fsl_qdma->block_number;
526 queue_temp->block_base = fsl_qdma->block_base +
527 FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, j);
585 static int fsl_qdma_halt(struct fsl_qdma_engine *fsl_qdma)
589 void __iomem *block, *ctrl = fsl_qdma->ctrl_base;
592 reg = qdma_readl(fsl_qdma, ctrl + FSL_QDMA_DMR);
594 qdma_writel(fsl_qdma, reg, ctrl + FSL_QDMA_DMR);
595 for (j = 0; j < fsl_qdma->block_number; j++) {
596 block = fsl_qdma->block_base +
597 FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, j);
599 qdma_writel(fsl_qdma, 0, block + FSL_QDMA_BCQMR(i));
602 reg = qdma_readl(fsl_qdma, ctrl + FSL_QDMA_DSR);
610 for (j = 0; j < fsl_qdma->block_number; j++) {
611 block = fsl_qdma->block_base +
612 FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, j);
615 qdma_writel(fsl_qdma, 0, block + FSL_QDMA_BSQMR);
621 qdma_writel(fsl_qdma, FSL_QDMA_BCQIDR_CLEAR,
629 fsl_qdma_queue_transfer_complete(struct fsl_qdma_engine *fsl_qdma,
639 struct fsl_qdma_queue *fsl_queue = fsl_qdma->queue;
640 struct fsl_qdma_queue *fsl_status = fsl_qdma->status[id];
646 reg = qdma_readl(fsl_qdma, block + FSL_QDMA_BSQSR);
658 id * fsl_qdma->n_queues;
682 reg = qdma_readl(fsl_qdma, block + FSL_QDMA_BSQMR);
689 qdma_writel(fsl_qdma, reg, block + FSL_QDMA_BSQMR);
697 reg = qdma_readl(fsl_qdma, block + FSL_QDMA_BSQMR);
703 qdma_writel(fsl_qdma, reg, block + FSL_QDMA_BSQMR);
725 dev_err(fsl_qdma->dma_dev.dev,
743 struct fsl_qdma_engine *fsl_qdma = dev_id;
744 void __iomem *status = fsl_qdma->status_base;
750 intr = qdma_readl(fsl_qdma, status + FSL_QDMA_DEDR);
753 decfdw0r = qdma_readl(fsl_qdma, status + FSL_QDMA_DECFDW0R);
754 decfdw1r = qdma_readl(fsl_qdma, status + FSL_QDMA_DECFDW1R);
755 decfdw2r = qdma_readl(fsl_qdma, status + FSL_QDMA_DECFDW2R);
756 decfdw3r = qdma_readl(fsl_qdma, status + FSL_QDMA_DECFDW3R);
757 dev_err(fsl_qdma->dma_dev.dev,
762 qdma_writel(fsl_qdma, FSL_QDMA_DEDR_CLEAR, status + FSL_QDMA_DEDR);
770 struct fsl_qdma_engine *fsl_qdma = dev_id;
771 void __iomem *block, *ctrl = fsl_qdma->ctrl_base;
773 id = irq - fsl_qdma->irq_base;
774 if (id < 0 && id > fsl_qdma->block_number) {
775 dev_err(fsl_qdma->dma_dev.dev,
777 irq, fsl_qdma->irq_base);
780 block = fsl_qdma->block_base +
781 FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, id);
783 intr = qdma_readl(fsl_qdma, block + FSL_QDMA_BCQIDR(0));
786 intr = fsl_qdma_queue_transfer_complete(fsl_qdma, block, id);
789 reg = qdma_readl(fsl_qdma, ctrl + FSL_QDMA_DMR);
791 qdma_writel(fsl_qdma, reg, ctrl + FSL_QDMA_DMR);
792 qdma_writel(fsl_qdma, 0, block + FSL_QDMA_BCQIER(0));
793 dev_err(fsl_qdma->dma_dev.dev, "QDMA: status err!\n");
797 qdma_writel(fsl_qdma, FSL_QDMA_BCQIDR_CLEAR,
805 struct fsl_qdma_engine *fsl_qdma)
812 fsl_qdma->error_irq =
814 if (fsl_qdma->error_irq < 0)
815 return fsl_qdma->error_irq;
817 ret = devm_request_irq(&pdev->dev, fsl_qdma->error_irq,
819 "qDMA error", fsl_qdma);
825 for (i = 0; i < fsl_qdma->block_number; i++) {
827 fsl_qdma->queue_irq[i] =
830 if (fsl_qdma->queue_irq[i] < 0)
831 return fsl_qdma->queue_irq[i];
834 fsl_qdma->queue_irq[i],
838 fsl_qdma);
846 ret = irq_set_affinity_hint(fsl_qdma->queue_irq[i],
852 fsl_qdma->queue_irq[i]);
861 struct fsl_qdma_engine *fsl_qdma)
865 devm_free_irq(&pdev->dev, fsl_qdma->error_irq, fsl_qdma);
866 for (i = 0; i < fsl_qdma->block_number; i++)
867 devm_free_irq(&pdev->dev, fsl_qdma->queue_irq[i], fsl_qdma);
870 static int fsl_qdma_reg_init(struct fsl_qdma_engine *fsl_qdma)
875 void __iomem *status = fsl_qdma->status_base;
876 void __iomem *block, *ctrl = fsl_qdma->ctrl_base;
877 struct fsl_qdma_queue *fsl_queue = fsl_qdma->queue;
880 ret = fsl_qdma_halt(fsl_qdma);
882 dev_err(fsl_qdma->dma_dev.dev, "DMA halt failed!");
886 for (i = 0; i < fsl_qdma->block_number; i++) {
892 block = fsl_qdma->block_base +
893 FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, i);
894 qdma_writel(fsl_qdma, FSL_QDMA_BCQIDR_CLEAR,
898 for (j = 0; j < fsl_qdma->block_number; j++) {
899 block = fsl_qdma->block_base +
900 FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, j);
901 for (i = 0; i < fsl_qdma->n_queues; i++) {
902 temp = fsl_queue + i + (j * fsl_qdma->n_queues);
911 qdma_writel(fsl_qdma, temp->bus_addr,
913 qdma_writel(fsl_qdma, temp->bus_addr,
920 qdma_writel(fsl_qdma, reg, block + FSL_QDMA_BCQMR(i));
929 qdma_writel(fsl_qdma, FSL_QDMA_SQCCMR_ENTER_WM,
939 qdma_writel(fsl_qdma, fsl_qdma->status[j]->bus_addr,
941 qdma_writel(fsl_qdma, fsl_qdma->status[j]->bus_addr,
944 qdma_writel(fsl_qdma, FSL_QDMA_BCQIER_CQTIE,
946 qdma_writel(fsl_qdma, FSL_QDMA_BSQICR_ICEN |
949 qdma_writel(fsl_qdma, FSL_QDMA_CQIER_MEIE |
956 (fsl_qdma->status[j]->n_cq) - 6);
958 qdma_writel(fsl_qdma, reg, block + FSL_QDMA_BSQMR);
959 reg = qdma_readl(fsl_qdma, block + FSL_QDMA_BSQMR);
963 qdma_writel(fsl_qdma, FSL_QDMA_DEDR_CLEAR, status + FSL_QDMA_DEDR);
964 qdma_writel(fsl_qdma, FSL_QDMA_DEIER_CLEAR, status + FSL_QDMA_DEIER);
966 reg = qdma_readl(fsl_qdma, ctrl + FSL_QDMA_DMR);
968 qdma_writel(fsl_qdma, reg, ctrl + FSL_QDMA_DMR);
1072 struct fsl_qdma_engine *fsl_qdma = fsl_chan->qdma;
1076 return fsl_qdma->desc_allocated;
1109 fsl_qdma->desc_allocated++;
1110 return fsl_qdma->desc_allocated;
1125 struct fsl_qdma_engine *fsl_qdma;
1148 len = sizeof(*fsl_qdma);
1149 fsl_qdma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
1150 if (!fsl_qdma)
1154 fsl_qdma->chans = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
1155 if (!fsl_qdma->chans)
1159 fsl_qdma->status = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
1160 if (!fsl_qdma->status)
1164 fsl_qdma->queue_irq = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
1165 if (!fsl_qdma->queue_irq)
1174 fsl_qdma->desc_allocated = 0;
1175 fsl_qdma->n_chans = chans;
1176 fsl_qdma->n_queues = queues;
1177 fsl_qdma->block_number = blk_num;
1178 fsl_qdma->block_offset = blk_off;
1180 mutex_init(&fsl_qdma->fsl_qdma_mutex);
1182 for (i = 0; i < fsl_qdma->block_number; i++) {
1183 fsl_qdma->status[i] = fsl_qdma_prep_status_queue(pdev);
1184 if (!fsl_qdma->status[i])
1187 fsl_qdma->ctrl_base = devm_platform_ioremap_resource(pdev, 0);
1188 if (IS_ERR(fsl_qdma->ctrl_base))
1189 return PTR_ERR(fsl_qdma->ctrl_base);
1191 fsl_qdma->status_base = devm_platform_ioremap_resource(pdev, 1);
1192 if (IS_ERR(fsl_qdma->status_base))
1193 return PTR_ERR(fsl_qdma->status_base);
1195 fsl_qdma->block_base = devm_platform_ioremap_resource(pdev, 2);
1196 if (IS_ERR(fsl_qdma->block_base))
1197 return PTR_ERR(fsl_qdma->block_base);
1198 fsl_qdma->queue = fsl_qdma_alloc_queue_resources(pdev, fsl_qdma);
1199 if (!fsl_qdma->queue)
1202 fsl_qdma->irq_base = platform_get_irq_byname(pdev, "qdma-queue0");
1203 if (fsl_qdma->irq_base < 0)
1204 return fsl_qdma->irq_base;
1206 fsl_qdma->feature = of_property_read_bool(np, "big-endian");
1207 INIT_LIST_HEAD(&fsl_qdma->dma_dev.channels);
1209 for (i = 0; i < fsl_qdma->n_chans; i++) {
1210 struct fsl_qdma_chan *fsl_chan = &fsl_qdma->chans[i];
1212 fsl_chan->qdma = fsl_qdma;
1213 fsl_chan->queue = fsl_qdma->queue + i % (fsl_qdma->n_queues *
1214 fsl_qdma->block_number);
1216 vchan_init(&fsl_chan->vchan, &fsl_qdma->dma_dev);
1219 dma_cap_set(DMA_MEMCPY, fsl_qdma->dma_dev.cap_mask);
1221 fsl_qdma->dma_dev.dev = &pdev->dev;
1222 fsl_qdma->dma_dev.device_free_chan_resources =
1224 fsl_qdma->dma_dev.device_alloc_chan_resources =
1226 fsl_qdma->dma_dev.device_tx_status = dma_cookie_status;
1227 fsl_qdma->dma_dev.device_prep_dma_memcpy = fsl_qdma_prep_memcpy;
1228 fsl_qdma->dma_dev.device_issue_pending = fsl_qdma_issue_pending;
1229 fsl_qdma->dma_dev.device_synchronize = fsl_qdma_synchronize;
1230 fsl_qdma->dma_dev.device_terminate_all = fsl_qdma_terminate_all;
1238 platform_set_drvdata(pdev, fsl_qdma);
1240 ret = fsl_qdma_reg_init(fsl_qdma);
1246 ret = fsl_qdma_irq_init(pdev, fsl_qdma);
1250 ret = dma_async_device_register(&fsl_qdma->dma_dev);
1273 struct fsl_qdma_engine *fsl_qdma = platform_get_drvdata(pdev);
1275 fsl_qdma_irq_exit(pdev, fsl_qdma);
1276 fsl_qdma_cleanup_vchan(&fsl_qdma->dma_dev);
1278 dma_async_device_unregister(&fsl_qdma->dma_dev);