Lines Matching defs:dma
11 #include <dt-bindings/dma/at91.h>
243 struct dma_device dma;
334 return container_of(ddev, struct at_xdmac, dma);
441 if (!list_empty(&atxdmac->dma.channels) && suspend_descriptors) {
442 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels,
520 * There is no end of list when doing cyclic dma, we need to get
641 struct device *dev = atxdmac->dma.dev;
644 dev_err(dev, "dma phandler args: bad number of args\n");
648 chan = dma_get_any_slave_channel(&atxdmac->dma);
650 dev_err(dev, "can't get a dma channel\n");
1840 dev_vdbg(atxdmac->dma.dev,
1848 for (i = 0; i < atxdmac->dma.chancnt; i++) {
1856 dev_vdbg(atxdmac->dma.dev,
2114 if (!of_property_read_u32(pdev->dev.of_node, "dma-requests",
2134 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
2154 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
2198 for (i = 0; i < atxdmac->dma.chancnt; i++) {
2205 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
2327 dev_err(&pdev->dev, "no memory for descriptors dma pool\n");
2332 dma_cap_set(DMA_CYCLIC, atxdmac->dma.cap_mask);
2333 dma_cap_set(DMA_INTERLEAVE, atxdmac->dma.cap_mask);
2334 dma_cap_set(DMA_MEMCPY, atxdmac->dma.cap_mask);
2335 dma_cap_set(DMA_MEMSET, atxdmac->dma.cap_mask);
2336 dma_cap_set(DMA_MEMSET_SG, atxdmac->dma.cap_mask);
2337 dma_cap_set(DMA_SLAVE, atxdmac->dma.cap_mask);
2342 dma_cap_set(DMA_PRIVATE, atxdmac->dma.cap_mask);
2343 atxdmac->dma.dev = &pdev->dev;
2344 atxdmac->dma.device_alloc_chan_resources = at_xdmac_alloc_chan_resources;
2345 atxdmac->dma.device_free_chan_resources = at_xdmac_free_chan_resources;
2346 atxdmac->dma.device_tx_status = at_xdmac_tx_status;
2347 atxdmac->dma.device_issue_pending = at_xdmac_issue_pending;
2348 atxdmac->dma.device_prep_dma_cyclic = at_xdmac_prep_dma_cyclic;
2349 atxdmac->dma.device_prep_interleaved_dma = at_xdmac_prep_interleaved;
2350 atxdmac->dma.device_prep_dma_memcpy = at_xdmac_prep_dma_memcpy;
2351 atxdmac->dma.device_prep_dma_memset = at_xdmac_prep_dma_memset;
2352 atxdmac->dma.device_prep_dma_memset_sg = at_xdmac_prep_dma_memset_sg;
2353 atxdmac->dma.device_prep_slave_sg = at_xdmac_prep_slave_sg;
2354 atxdmac->dma.device_config = at_xdmac_device_config;
2355 atxdmac->dma.device_pause = at_xdmac_device_pause;
2356 atxdmac->dma.device_resume = at_xdmac_device_resume;
2357 atxdmac->dma.device_terminate_all = at_xdmac_device_terminate_all;
2358 atxdmac->dma.src_addr_widths = AT_XDMAC_DMA_BUSWIDTHS;
2359 atxdmac->dma.dst_addr_widths = AT_XDMAC_DMA_BUSWIDTHS;
2360 atxdmac->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
2361 atxdmac->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
2372 INIT_LIST_HEAD(&atxdmac->dma.channels);
2380 atchan->chan.device = &atxdmac->dma;
2382 &atxdmac->dma.channels);
2397 ret = dma_async_device_register(&atxdmac->dma);
2406 dev_err(&pdev->dev, "could not register of dma controller\n");
2421 dma_async_device_unregister(&atxdmac->dma);
2441 dma_async_device_unregister(&atxdmac->dma);
2449 for (i = 0; i < atxdmac->dma.chancnt; i++) {
2468 .compatible = "atmel,sama5d4-dma",
2471 .compatible = "microchip,sama7g5-dma",