Lines Matching refs:no
89 unsigned int no;
258 if (direction != admac_chan_direction(adchan->no))
392 residue = admac_cyclic_read_residue(ad, adchan->no, adtx);
412 u32 startbit = 1 << (adchan->no / 2);
415 ad->base + REG_CHAN_INTSTATUS(adchan->no, ad->irq_index));
417 ad->base + REG_CHAN_INTMASK(adchan->no, ad->irq_index));
419 switch (admac_chan_direction(adchan->no)) {
429 dev_dbg(adchan->host->dev, "ch%d start\n", adchan->no);
435 u32 stopbit = 1 << (adchan->no / 2);
437 switch (admac_chan_direction(adchan->no)) {
447 dev_dbg(adchan->host->dev, "ch%d stop\n", adchan->no);
455 ad->base + REG_CHAN_CTL(adchan->no));
456 writel_relaxed(0, ad->base + REG_CHAN_CTL(adchan->no));
462 int ch = adchan->no;
559 ret = admac_alloc_sram_carveout(ad, admac_chan_direction(adchan->no),
565 ad->base + REG_CHAN_SRAM_CARVEOUT(adchan->no));
575 admac_free_sram_carveout(adchan->host, admac_chan_direction(adchan->no),
668 static void admac_handle_chan_int(struct admac_data *ad, int no)
670 u32 cause = readl_relaxed(ad->base + REG_CHAN_INTSTATUS(no, ad->irq_index));
673 admac_handle_status_err(ad, no);
676 admac_handle_status_desc_done(ad, no);
743 bool is_tx = admac_chan_direction(adchan->no) == DMA_MEM_TO_DEV;
745 u32 bus_width = readl_relaxed(ad->base + REG_BUS_WIDTH(adchan->no)) &
785 writel_relaxed(bus_width, ad->base + REG_BUS_WIDTH(adchan->no));
796 ad->base + REG_CHAN_FIFOCTL(adchan->no));
837 return dev_err_probe(&pdev->dev, irq, "no usable interrupt\n");
880 adchan->no = i;