Lines Matching refs:base
124 __iomem void *base;
187 u32 base = FIELD_GET(CHAN_SRAM_CARVEOUT_BASE, carveout);
195 if (WARN_ON(base >= sram->size))
199 i = base / SRAM_BLOCK;
206 void __iomem *addr = ad->base + reg;
298 writel_relaxed(lower_32_bits(addr), ad->base + REG_DESC_WRITE(channo));
299 writel_relaxed(upper_32_bits(addr), ad->base + REG_DESC_WRITE(channo));
300 writel_relaxed(tx->period_len, ad->base + REG_DESC_WRITE(channo));
301 writel_relaxed(FLAG_DESC_NOTIFY, ad->base + REG_DESC_WRITE(channo));
317 if (readl_relaxed(ad->base + REG_DESC_RING(channo)) & RING_FULL)
351 ring1 = readl_relaxed(ad->base + REG_REPORT_RING(channo));
352 residue1 = readl_relaxed(ad->base + REG_RESIDUE(channo));
353 ring2 = readl_relaxed(ad->base + REG_REPORT_RING(channo));
354 residue2 = readl_relaxed(ad->base + REG_RESIDUE(channo));
415 ad->base + REG_CHAN_INTSTATUS(adchan->no, ad->irq_index));
417 ad->base + REG_CHAN_INTMASK(adchan->no, ad->irq_index));
421 writel_relaxed(startbit, ad->base + REG_TX_START);
424 writel_relaxed(startbit, ad->base + REG_RX_START);
439 writel_relaxed(stopbit, ad->base + REG_TX_STOP);
442 writel_relaxed(stopbit, ad->base + REG_RX_STOP);
455 ad->base + REG_CHAN_CTL(adchan->no));
456 writel_relaxed(0, ad->base + REG_CHAN_CTL(adchan->no));
465 writel_relaxed(0, ad->base + REG_CHAN_CTL(ch));
565 ad->base + REG_CHAN_SRAM_CARVEOUT(adchan->no));
605 if (readl_relaxed(ad->base + REG_REPORT_RING(channo)) & RING_EMPTY)
608 countval_lo = readl_relaxed(ad->base + REG_REPORT_READ(channo));
609 countval_hi = readl_relaxed(ad->base + REG_REPORT_READ(channo));
610 unk1 = readl_relaxed(ad->base + REG_REPORT_READ(channo));
611 flags = readl_relaxed(ad->base + REG_REPORT_READ(channo));
624 if (readl_relaxed(ad->base + REG_DESC_RING(channo)) & RING_ERR) {
625 writel_relaxed(RING_ERR, ad->base + REG_DESC_RING(channo));
630 if (readl_relaxed(ad->base + REG_REPORT_RING(channo)) & RING_ERR) {
631 writel_relaxed(RING_ERR, ad->base + REG_REPORT_RING(channo));
650 ad->base + REG_CHAN_INTSTATUS(channo, ad->irq_index));
670 u32 cause = readl_relaxed(ad->base + REG_CHAN_INTSTATUS(no, ad->irq_index));
685 rx_intstate = readl_relaxed(ad->base + REG_RX_INTSTATE(ad->irq_index));
686 tx_intstate = readl_relaxed(ad->base + REG_TX_INTSTATE(ad->irq_index));
687 global_intstate = readl_relaxed(ad->base + REG_GLOBAL_INTSTATE(ad->irq_index));
707 writel_relaxed(~(u32) 0, ad->base + REG_GLOBAL_INTSTATE(ad->irq_index));
745 u32 bus_width = readl_relaxed(ad->base + REG_BUS_WIDTH(adchan->no)) &
785 writel_relaxed(bus_width, ad->base + REG_BUS_WIDTH(adchan->no));
796 ad->base + REG_CHAN_FIFOCTL(adchan->no));
840 ad->base = devm_platform_ioremap_resource(pdev, 0);
841 if (IS_ERR(ad->base))
842 return dev_err_probe(&pdev->dev, PTR_ERR(ad->base),
915 ad->txcache.size = readl_relaxed(ad->base + REG_TX_SRAM_SIZE);
916 ad->rxcache.size = readl_relaxed(ad->base + REG_RX_SRAM_SIZE);
920 readl_relaxed(ad->base + REG_IMPRINT), ad->txcache.size, ad->rxcache.size);