Lines Matching defs:channo
222 static enum dma_transfer_direction admac_chan_direction(int channo)
225 return (channo & 1) ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
285 static void admac_cyclic_write_one_desc(struct admac_data *ad, int channo,
296 channo, &addr, tx->period_len, FLAG_DESC_NOTIFY);
298 writel_relaxed(lower_32_bits(addr), ad->base + REG_DESC_WRITE(channo));
299 writel_relaxed(upper_32_bits(addr), ad->base + REG_DESC_WRITE(channo));
300 writel_relaxed(tx->period_len, ad->base + REG_DESC_WRITE(channo));
301 writel_relaxed(FLAG_DESC_NOTIFY, ad->base + REG_DESC_WRITE(channo));
311 static void admac_cyclic_write_desc(struct admac_data *ad, int channo,
317 if (readl_relaxed(ad->base + REG_DESC_RING(channo)) & RING_FULL)
319 admac_cyclic_write_one_desc(ad, channo, tx);
343 static u32 admac_cyclic_read_residue(struct admac_data *ad, int channo,
351 ring1 = readl_relaxed(ad->base + REG_REPORT_RING(channo));
352 residue1 = readl_relaxed(ad->base + REG_RESIDUE(channo));
353 ring2 = readl_relaxed(ad->base + REG_REPORT_RING(channo));
354 residue2 = readl_relaxed(ad->base + REG_RESIDUE(channo));
598 static int admac_drain_reports(struct admac_data *ad, int channo)
605 if (readl_relaxed(ad->base + REG_REPORT_RING(channo)) & RING_EMPTY)
608 countval_lo = readl_relaxed(ad->base + REG_REPORT_READ(channo));
609 countval_hi = readl_relaxed(ad->base + REG_REPORT_READ(channo));
610 unk1 = readl_relaxed(ad->base + REG_REPORT_READ(channo));
611 flags = readl_relaxed(ad->base + REG_REPORT_READ(channo));
614 channo, ((u64) countval_hi) << 32 | countval_lo, unk1, flags);
620 static void admac_handle_status_err(struct admac_data *ad, int channo)
624 if (readl_relaxed(ad->base + REG_DESC_RING(channo)) & RING_ERR) {
625 writel_relaxed(RING_ERR, ad->base + REG_DESC_RING(channo));
626 dev_err_ratelimited(ad->dev, "ch%d descriptor ring error\n", channo);
630 if (readl_relaxed(ad->base + REG_REPORT_RING(channo)) & RING_ERR) {
631 writel_relaxed(RING_ERR, ad->base + REG_REPORT_RING(channo));
632 dev_err_ratelimited(ad->dev, "ch%d report ring error\n", channo);
637 dev_err(ad->dev, "ch%d unknown error, masking errors as cause of IRQs\n", channo);
638 admac_modify(ad, REG_CHAN_INTMASK(channo, ad->irq_index),
643 static void admac_handle_status_desc_done(struct admac_data *ad, int channo)
645 struct admac_chan *adchan = &ad->channels[channo];
650 ad->base + REG_CHAN_INTSTATUS(channo, ad->irq_index));
653 nreports = admac_drain_reports(ad, channo);
662 admac_cyclic_write_desc(ad, channo, tx);