Lines Matching defs:lli
392 struct pl08x_phy_chan *phychan, const u32 *lli, u32 ccfg)
398 phychan->id, lli[PL080_LLI_SRC], lli[PL080_LLI_DST],
399 lli[PL080_LLI_LLI], lli[PL080_LLI_CCTL],
400 lli[PL080S_LLI_CCTL2], ccfg);
405 phychan->id, lli[PL080_LLI_SRC], lli[PL080_LLI_DST],
406 lli[PL080_LLI_LLI], lli[PL080_LLI_CCTL], ccfg);
408 writel_relaxed(lli[PL080_LLI_SRC], phychan->reg_src);
409 writel_relaxed(lli[PL080_LLI_DST], phychan->reg_dst);
410 writel_relaxed(lli[PL080_LLI_LLI], phychan->reg_lli);
419 u32 llictl = lli[PL080_LLI_CCTL];
510 writel_relaxed(lli[PL080_LLI_CCTL], phychan->reg_control);
515 writel_relaxed(lli[PL080S_LLI_CCTL2],
1223 "lli", "", "csrc", "cdst", "clli", "cctl", "cctl2");
1236 "lli", "", "csrc", "cdst", "clli", "cctl");
1325 * Here, Obviously as DMA controller doesn't know when a lli's
1326 * transfer gets over, it can't load next lli. So in this
1327 * case, there has to be an assumption that only one lli is
1405 "%s max bytes per lli = %zu\n",
1432 "%s fill lli with single lli chunk of "
1458 "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n",
2579 if (of_property_read_bool(np, "lli-bus-interface-ahb1"))
2581 if (of_property_read_bool(np, "lli-bus-interface-ahb2"))