Lines Matching defs:cctl
192 * @cctl: control reg values for current txd
203 /* Default cctl value for LLIs */
204 u32 cctl;
397 "clli=0x%08x, cctl=0x%08x, cctl2=0x%08x, ccfg=0x%08x\n",
404 "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n",
968 u32 cctl,
975 val = (cctl & FTDMAC020_LLI_SRC_WIDTH_MSK) >>
978 val = (cctl & FTDMAC020_LLI_DST_WIDTH_MSK) >>
982 val = (cctl & PL080_CONTROL_SWIDTH_MASK) >>
985 val = (cctl & PL080_CONTROL_DWIDTH_MASK) >>
1004 u32 cctl,
1008 u32 retbits = cctl;
1127 u32 cctl)
1140 dst_incr = !!(cctl & PL080_CONTROL_DST_INCR);
1141 src_incr = !!(cctl & PL080_CONTROL_SRC_INCR);
1170 int num_llis, int len, u32 cctl, u32 cctl2)
1185 llis_va[PL080_LLI_CCTL] = cctl;
1194 if (cctl & PL080_CONTROL_SRC_INCR)
1196 if (cctl & PL080_CONTROL_DST_INCR)
1206 struct pl08x_lli_build_data *bd, u32 *cctl, u32 len,
1209 *cctl = pl08x_lli_control_bits(pl08x, *cctl, 1, 1, len);
1210 pl08x_fill_lli_for_desc(pl08x, bd, num_llis, len, *cctl, len);
1223 "lli", "", "csrc", "cdst", "clli", "cctl", "cctl2");
1236 "lli", "", "csrc", "cdst", "clli", "cctl");
1263 u32 cctl, early_bytes = 0;
1276 cctl = txd->cctl;
1279 bd.srcbus.maxwidth = pl08x_get_bytes_for_lli(pl08x, cctl, true);
1282 bd.dstbus.maxwidth = pl08x_get_bytes_for_lli(pl08x, cctl, false);
1286 cctl = txd->cctl;
1294 pl08x_choose_master_bus(pl08x, &bd, &mbus, &sbus, cctl);
1299 cctl & PL080_CONTROL_SRC_INCR ? "+" : "",
1302 cctl & PL080_CONTROL_DST_INCR ? "+" : "",
1355 cctl = pl08x_lli_control_bits(pl08x, cctl,
1359 0, cctl, 0);
1381 prep_byte_width_lli(pl08x, &bd, &cctl, early_bytes,
1436 cctl = pl08x_lli_control_bits(pl08x, cctl,
1440 lli_len, cctl, tsize);
1451 prep_byte_width_lli(pl08x, &bd, &cctl,
1644 u32 cctl = 0;
1658 cctl |= dst_ahb2;
1660 cctl |= src_ahb2;
1662 return cctl;
1665 static u32 pl08x_cctl(u32 cctl)
1667 cctl &= ~(PL080_CONTROL_SRC_AHB2 | PL080_CONTROL_DST_AHB2 |
1672 return cctl | PL080_CONTROL_PROT_SYS;
1703 u32 width, burst, cctl = 0;
1709 cctl |= width << PL080_CONTROL_SWIDTH_SHIFT;
1710 cctl |= width << PL080_CONTROL_DWIDTH_SHIFT;
1721 cctl |= burst << PL080_CONTROL_SB_SIZE_SHIFT;
1722 cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT;
1724 return pl08x_cctl(cctl);
1755 u32 cctl = 0;
1757 /* Conjure cctl */
1764 cctl |= PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT |
1768 cctl |= PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT |
1772 cctl |= PL080_BSIZE_8 << PL080_CONTROL_SB_SIZE_SHIFT |
1776 cctl |= PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT |
1780 cctl |= PL080_BSIZE_32 << PL080_CONTROL_SB_SIZE_SHIFT |
1784 cctl |= PL080_BSIZE_64 << PL080_CONTROL_SB_SIZE_SHIFT |
1788 cctl |= PL080_BSIZE_128 << PL080_CONTROL_SB_SIZE_SHIFT |
1792 cctl |= PL080_BSIZE_256 << PL080_CONTROL_SB_SIZE_SHIFT |
1803 cctl |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT |
1807 cctl |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT |
1811 cctl |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT |
1818 cctl |= PL080_CONTROL_PROT_BUFF;
1820 cctl |= PL080_CONTROL_PROT_CACHE;
1823 cctl |= PL080_CONTROL_PROT_SYS;
1826 cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR;
1829 cctl |= pl08x_select_bus(false,
1833 return cctl;
1838 u32 cctl = 0;
1840 /* Conjure cctl */
1847 cctl |= PL080_WIDTH_8BIT << FTDMAC020_LLI_SRC_WIDTH_SHIFT |
1851 cctl |= PL080_WIDTH_16BIT << FTDMAC020_LLI_SRC_WIDTH_SHIFT |
1855 cctl |= PL080_WIDTH_32BIT << FTDMAC020_LLI_SRC_WIDTH_SHIFT |
1864 cctl |= FTDMAC020_LLI_TC_MSK;
1871 cctl |= pl08x_select_bus(true,
1875 return cctl;
1911 txd->cctl = pl08x_ftdmac020_memcpy_cctl(pl08x);
1916 txd->cctl = pl08x_memcpy_cctl(pl08x);
1939 u32 maxburst, cctl;
1953 cctl = PL080_CONTROL_SRC_INCR;
1960 cctl = PL080_CONTROL_DST_INCR;
1973 cctl |= pl08x_get_cctl(plchan, addr_width, maxburst);
1974 if (cctl == ~0) {
1981 txd->cctl = cctl | pl08x_select_bus(false, src_buses, dst_buses);
2105 txd->cctl |= PL080_CONTROL_TC_IRQ_EN;