Lines Matching defs:CXL
21 * This implements the PCI exclusive functionality for a CXL device as it is
22 * defined by the Compute Express Link specification. CXL devices may surface
23 * certain functionality even if it isn't CXL enabled. While this driver is
24 * focused around the PCI specific aspects of a CXL device, it binds to the
25 * specific CXL memory device class code, and therefore the implementation of
26 * cxl_pci is focused around CXL memory devices.
29 * - Create the memX device and register on the CXL bus.
32 * - Registers a CXL mailbox with cxl_core.
39 /* CXL 2.0 - 8.2.8.4 */
43 * CXL 2.0 ECN "Add Mailbox Ready Time" defines a capability field to
49 * until someone builds a CXL device that needs more time in practice.
179 * This is a generic form of the CXL mailbox send command thus only using the
180 * registers defined by the mailbox capability ID - CXL 2.0 8.2.8.4. Memory
181 * devices, and perhaps other types of CXL devices may have further information
185 * The CXL spec allows for up to two mailboxes. The intention is for the primary
204 * Here are the steps from 8.2.8.4 of the CXL 2.0 spec.
421 * CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register
461 * Assume that any RCIEP that emits the CXL memory expander class code
592 * Per CXL 3.0 3.1.1 CXL.io Endpoint a function on a CXL device must
594 * CXL.cache or CXL.mem.
618 * CXL 3.0 8.2.8.3.1: The lower 32 bits are the status;
748 * When BIOS maintains CXL error reporting control, it will process
813 "Device DVSEC not present, skip CXL.mem init\n");
924 /* PCI class code for CXL.mem Type-3 Devices */
936 dev_info(&pdev->dev, "%s: restart CXL.mem after slot reset\n",
973 MODULE_IMPORT_NS(CXL);