Lines Matching defs:host
21 * Find a targets entry (n) in the host bridge interleave list.
326 __mock struct acpi_device *to_cxl_host_bridge(struct device *host,
407 struct device *host = root_port->dev.parent;
408 struct acpi_device *hb = to_cxl_host_bridge(host, match);
434 * VH mode it will be bound to the CXL host bridge's port
454 * A host bridge is a dport to a CFMWS decode and it is a uport to the
455 * dport (PCIe Root Ports) in the host bridge.
460 struct device *host = root_port->dev.parent;
461 struct acpi_device *hb = to_cxl_host_bridge(host, match);
477 dev_dbg(host, "host bridge expected and not found\n");
482 dev_info(bridge, "host supports CXL (restricted)\n");
501 rc = devm_cxl_register_pci_bus(host, bridge, pci_root->bus);
505 port = devm_cxl_add_port(host, bridge, component_reg_phys, dport);
509 dev_info(bridge, "host supports CXL\n");
519 struct device *host = root_port->dev.parent;
528 cxl_nvb = devm_cxl_add_nvdimm_bridge(host, root_port);
530 dev_dbg(host, "failed to register pmem\n");
533 dev_dbg(host, "%s: add: %s\n", dev_name(&root_port->dev),
667 struct device *host = &pdev->dev;
668 struct acpi_device *adev = ACPI_COMPANION(host);
677 cxl_res = devm_kzalloc(host, sizeof(*cxl_res), GFP_KERNEL);
685 root_port = devm_cxl_add_port(host, host, CXL_RESOURCE_NONE, NULL);
694 rc = devm_add_action_or_reset(host, remove_cxl_resources, cxl_res);
699 .dev = host,
718 * Root level scanned with host-bridge as dports, now scan host-bridges