Lines Matching refs:val
64 u32 val;
69 val = readl(priv->base + EIP197_CS_RAM_CTRL);
70 val = (val & ~EIP197_CS_BANKSEL_MASK) |
72 writel(val, priv->base + EIP197_CS_RAM_CTRL);
80 u32 val, addrhi, addrlo, addrmid, addralias, delta, marker;
112 val = readl(priv->base + EIP197_CLASSIFICATION_RAMS +
115 if ((val & probemask) == marker)
129 u32 htable_offset, val, offset;
139 val = EIP197_CS_RC_NEXT(i + 1) | EIP197_CS_RC_PREV(i - 1);
141 val |= EIP197_CS_RC_PREV(EIP197_RC_NULL);
143 val |= EIP197_CS_RC_NEXT(EIP197_RC_NULL);
144 writel(val, priv->base + offset + 4);
160 u32 val, dsize, asize;
172 val = readl(priv->base + EIP197_CS_RAM_CTRL);
173 val &= ~EIP197_TRC_ENABLE_MASK;
174 val |= EIP197_TRC_ENABLE_0 | EIP197_CS_BANKSEL_MASK;
175 writel(val, priv->base + EIP197_CS_RAM_CTRL);
176 val = readl(priv->base + EIP197_CS_RAM_CTRL);
177 maxbanks = ((val&EIP197_CS_BANKSEL_MASK)>>EIP197_CS_BANKSEL_OFS) + 1;
186 val = readl(priv->base + EIP197_TRC_PARAMS);
187 val |= EIP197_TRC_PARAMS_SW_RESET | EIP197_TRC_PARAMS_DATA_ACCESS;
188 writel(val, priv->base + EIP197_TRC_PARAMS);
198 val = readl(priv->base + EIP197_TRC_PARAMS);
200 val &= ~(EIP197_TRC_PARAMS_DATA_ACCESS | EIP197_CS_BANKSEL_MASK);
201 writel(val, priv->base + EIP197_TRC_PARAMS);
244 val = readl(priv->base + EIP197_CS_RAM_CTRL);
245 val &= ~EIP197_TRC_ENABLE_MASK;
246 writel(val, priv->base + EIP197_CS_RAM_CTRL);
249 val = EIP197_TRC_FREECHAIN_HEAD_PTR(0) |
251 writel(val, priv->base + EIP197_TRC_FREECHAIN);
254 val = EIP197_TRC_PARAMS2_RC_SZ_SMALL(cs_trc_rec_wc) |
256 writel(val, priv->base + EIP197_TRC_PARAMS2);
259 val = EIP197_TRC_PARAMS_RC_SZ_LARGE(cs_trc_lg_rec_wc) |
262 writel(val, priv->base + EIP197_TRC_PARAMS);
272 u32 val;
280 val = readl(EIP197_PE(priv) + EIP197_PE_ICE_SCRATCH_CTRL(pe));
281 val |= EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_TIMER |
285 writel(val, EIP197_PE(priv) + EIP197_PE_ICE_SCRATCH_CTRL(pe));
319 u32 val;
325 val = le32_to_cpu(((const __le32 *)fw->data)[i]);
327 val = be32_to_cpu(((const __be32 *)fw->data)[i]);
329 writel(val,
331 i * sizeof(val));
373 u32 val;
381 val = 0;
383 val = EIP197_PE_ICE_UENG_START_OFFSET((ifppsz - 1) &
386 writel(val, EIP197_PE(priv) + EIP197_PE_ICE_FPP_CTRL(pe));
390 val = 0;
392 val = EIP197_PE_ICE_UENG_START_OFFSET((ipuesz - 1) &
395 writel(val, EIP197_PE(priv) + EIP197_PE_ICE_PUE_CTRL(pe));
484 u32 cd_size_rnd, val;
526 val = EIP197_HIA_xDR_CFG_WR_CACHE(WR_CACHE_3BITS);
527 val |= EIP197_HIA_xDR_CFG_RD_CACHE(RD_CACHE_3BITS);
528 writel(val, EIP197_HIA_CDR(priv, i) + EIP197_HIA_xDR_DMA_CFG);
540 u32 rd_size_rnd, val;
575 val = EIP197_HIA_xDR_CFG_WR_CACHE(WR_CACHE_3BITS);
576 val |= EIP197_HIA_xDR_CFG_RD_CACHE(RD_CACHE_3BITS);
577 val |= EIP197_HIA_xDR_WR_RES_BUF | EIP197_HIA_xDR_WR_CTRL_BUF;
578 writel(val,
586 val = readl(EIP197_HIA_AIC_R(priv) + EIP197_HIA_AIC_R_ENABLE_CTRL(i));
587 val |= EIP197_RDR_IRQ(i);
588 writel(val, EIP197_HIA_AIC_R(priv) + EIP197_HIA_AIC_R_ENABLE_CTRL(i));
596 u32 val;
607 val = readl(EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL);
608 val |= EIP197_MST_CTRL_TX_MAX_CMD(5);
609 writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL);
639 val = EIP197_HIA_DFE_CFG_DIS_DEBUG;
640 val |= EIP197_HIA_DxE_CFG_MIN_DATA_SIZE(6) |
642 val |= EIP197_HIA_DxE_CFG_MIN_CTRL_SIZE(6) |
644 val |= EIP197_HIA_DxE_CFG_DATA_CACHE_CTRL(RD_CACHE_3BITS);
645 val |= EIP197_HIA_DxE_CFG_CTRL_CACHE_CTRL(RD_CACHE_3BITS);
646 writel(val, EIP197_HIA_DFE(priv) + EIP197_HIA_DFE_CFG(pe));
684 val = EIP197_HIA_DSE_CFG_DIS_DEBUG;
685 val |= EIP197_HIA_DxE_CFG_MIN_DATA_SIZE(opbuflo) |
687 val |= EIP197_HIA_DxE_CFG_DATA_CACHE_CTRL(WR_CACHE_3BITS);
688 val |= EIP197_HIA_DSE_CFG_ALWAYS_BUFFERABLE;
693 val |= EIP197_HIA_DSE_CFG_EN_SINGLE_WR;
694 writel(val, EIP197_HIA_DSE(priv) + EIP197_HIA_DSE_CFG(pe));
707 val = EIP197_PE_EIP96_TOKEN_CTRL_CTX_UPDATES |
710 writel(val, EIP197_PE(priv) + EIP197_PE_EIP96_TOKEN_CTRL(pe));
1399 u32 peid, version, mask, val, hiaopt, hwopt, peopt;
1449 val = readl(EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL);
1450 val = val ^ (mask >> 24); /* toggle byte swap bits */
1451 writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL);
1893 u32 val;
1933 val = readl(pciebase + EIP197_XLX_IRQ_BLOCK_ID_ADDR);
1934 if ((val >> 16) == EIP197_XLX_IRQ_BLOCK_ID_VALUE) {
1936 (val & 0xff));
1953 val);