Lines Matching defs:version
419 if (priv->data->version == EIP197D_MRVL)
421 else if (priv->data->version == EIP197B_MRVL ||
422 priv->data->version == EIP197_DEVBRD)
424 else if (priv->data->version == EIP197C_MXL)
434 if (minifw || priv->data->version != EIP197B_MRVL)
1399 u32 peid, version, mask, val, hiaopt, hwopt, peopt;
1409 * First try the EIP97 HIA version regs
1413 version = readl(priv->base + EIP97_HIA_AIC_BASE + EIP197_HIA_VERSION);
1416 if (EIP197_REG_LO16(version) == EIP197_HIA_VERSION_LE) {
1417 priv->hwconfig.hiaver = EIP197_VERSION_MASK(version);
1418 } else if (EIP197_REG_HI16(version) == EIP197_HIA_VERSION_BE) {
1421 priv->hwconfig.hiaver = EIP197_VERSION_SWAP(version);
1424 version = readl(priv->base + EIP197_HIA_AIC_BASE +
1426 if (EIP197_REG_LO16(version) == EIP197_HIA_VERSION_LE) {
1427 priv->hwconfig.hiaver = EIP197_VERSION_MASK(version);
1429 } else if (EIP197_REG_HI16(version) ==
1433 priv->hwconfig.hiaver = EIP197_VERSION_SWAP(version);
1444 * If the version was read byte-swapped, we need to flip the device
1459 version = readl(EIP197_GLOBAL(priv) + EIP197_VERSION);
1461 (EIP197_REG_LO16(version) != EIP197_VERSION_LE) &&
1462 (EIP197_REG_LO16(version) != EIP196_VERSION_LE)) ||
1464 (EIP197_REG_LO16(version) != EIP97_VERSION_LE)))) {
1470 version);
1474 priv->hwconfig.hwver = EIP197_VERSION_MASK(version);
1475 hwctg = version >> 28;
1476 peid = version & 255;
1479 version = readl(EIP197_PE(priv) + + EIP197_PE_VERSION(0));
1480 if (EIP197_REG_LO16(version) != EIP206_VERSION_LE) {
1484 priv->hwconfig.ppver = EIP197_VERSION_MASK(version);
1486 /* Detect EIP96 packet engine and version */
1487 version = readl(EIP197_PE(priv) + EIP197_PE_EIP96_VERSION(0));
1488 if (EIP197_REG_LO16(version) != EIP96_VERSION_LE) {
1492 priv->hwconfig.pever = EIP197_VERSION_MASK(version);
1520 /* Detect ICE EIP207 class. engine and version */
1521 version = readl(EIP197_PE(priv) +
1523 if (EIP197_REG_LO16(version) != EIP207_VERSION_LE) {
1528 priv->hwconfig.icever = EIP197_VERSION_MASK(version);
1532 /* Detect EIP96PP packet stream editor and version */
1533 version = readl(EIP197_PE(priv) + EIP197_PE_PSE_VERSION(0));
1534 if (EIP197_REG_LO16(version) != EIP96_VERSION_LE) {
1538 priv->hwconfig.psever = EIP197_VERSION_MASK(version);
1539 /* Detect OCE EIP207 class. engine and version */
1540 version = readl(EIP197_PE(priv) +
1542 if (EIP197_REG_LO16(version) != EIP207_VERSION_LE) {
1547 priv->hwconfig.ocever = EIP197_VERSION_MASK(version);
1569 version = readl(EIP197_HIA_AIC_R(priv) +
1571 if (EIP197_REG_LO16(version) != EIP201_VERSION_LE)
1597 if (IS_ENABLED(CONFIG_PCI) && priv->data->version == EIP197_DEVBRD) {
1824 .version = EIP97IES_MRVL,
1828 .version = EIP197B_MRVL,
1832 .version = EIP197D_MRVL,
1836 .version = EIP197_DEVBRD,
1840 .version = EIP197C_MXL,
1923 if (priv->data->version == EIP197_DEVBRD) {
1935 dev_dbg(dev, "Detected Xilinx PCIE IRQ block version %d, multiple MSI support enabled\n",