Lines Matching defs:base
45 writel(0, priv->base + EIP197_FLUE_IFC_LUT(i));
52 writel(0, priv->base + EIP197_FLUE_CACHEBASE_LO(i));
53 writel(0, priv->base + EIP197_FLUE_CACHEBASE_HI(i));
55 priv->base + EIP197_FLUE_CONFIG(i));
57 writel(0, priv->base + EIP197_FLUE_OFFSETS);
58 writel(0, priv->base + EIP197_FLUE_ARC4_OFFSET);
69 val = readl(priv->base + EIP197_CS_RAM_CTRL);
72 writel(val, priv->base + EIP197_CS_RAM_CTRL);
96 priv->base + EIP197_CLASSIFICATION_RAMS +
105 priv->base + EIP197_CLASSIFICATION_RAMS +
112 val = readl(priv->base + EIP197_CLASSIFICATION_RAMS +
137 priv->base + offset);
144 writel(val, priv->base + offset + 4);
146 writel(0, priv->base + offset + 8);
147 writel(0, priv->base + offset + 12);
154 priv->base + EIP197_CLASSIFICATION_RAMS +
172 val = readl(priv->base + EIP197_CS_RAM_CTRL);
175 writel(val, priv->base + EIP197_CS_RAM_CTRL);
176 val = readl(priv->base + EIP197_CS_RAM_CTRL);
180 writel(0, priv->base + EIP197_TRC_ECCCTRL);
186 val = readl(priv->base + EIP197_TRC_PARAMS);
188 writel(val, priv->base + EIP197_TRC_PARAMS);
198 val = readl(priv->base + EIP197_TRC_PARAMS);
201 writel(val, priv->base + EIP197_TRC_PARAMS);
207 writel(0, priv->base + EIP197_TRC_ECCCTRL);
244 val = readl(priv->base + EIP197_CS_RAM_CTRL);
246 writel(val, priv->base + EIP197_CS_RAM_CTRL);
251 writel(val, priv->base + EIP197_TRC_FREECHAIN);
256 writel(val, priv->base + EIP197_TRC_PARAMS2);
262 writel(val, priv->base + EIP197_TRC_PARAMS);
330 priv->base + EIP197_CLASSIFICATION_RAMS +
345 u32 base, pollofs;
353 base = EIP197_PE_ICE_SCRATCH_RAM(pe);
356 (readl_relaxed(EIP197_PE(priv) + base +
511 /* ring base address */
559 /* ring base address */
785 priv->base + EIP197_STRC_CONFIG);
1270 /* Do we have all required base algorithms available? */
1291 /* Do we have all required base algorithms available? */
1313 /* Do we have all required base algorithms available? */
1413 version = readl(priv->base + EIP97_HIA_AIC_BASE + EIP197_HIA_VERSION);
1424 version = readl(priv->base + EIP197_HIA_AIC_BASE +
1725 /* Reset the CDR base address */
1729 /* Reset the RDR base address */
1752 priv->base = devm_platform_ioremap_resource(pdev, 0);
1753 if (IS_ERR(priv->base)) {
1755 return PTR_ERR(priv->base);
1921 priv->base = pcim_iomap_table(pdev)[0];
1959 writel(1, priv->base + EIP197_XLX_GPIO_BASE);
1962 writel(0, priv->base + EIP197_XLX_GPIO_BASE);