Lines Matching refs:qm
368 struct hisi_qm *qm = s->private;
370 hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs,
461 bool hisi_zip_alg_support(struct hisi_qm *qm, u32 alg)
465 cap_val = qm->cap_tables.dev_cap_table[ZIP_DRV_ALG_BITMAP_IDX].cap_val;
472 static int hisi_zip_set_high_perf(struct hisi_qm *qm)
477 val = readl_relaxed(qm->io_base + HZIP_HIGH_PERF_OFFSET);
484 writel(val, qm->io_base + HZIP_HIGH_PERF_OFFSET);
485 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_HIGH_PERF_OFFSET,
489 pci_err(qm->pdev, "failed to set perf mode\n");
494 static void hisi_zip_open_sva_prefetch(struct hisi_qm *qm)
499 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps))
503 val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG);
505 writel(val, qm->io_base + HZIP_PREFETCH_CFG);
507 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_PREFETCH_CFG,
511 pci_err(qm->pdev, "failed to open sva prefetch\n");
514 static void hisi_zip_close_sva_prefetch(struct hisi_qm *qm)
519 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps))
522 val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG);
524 writel(val, qm->io_base + HZIP_PREFETCH_CFG);
526 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_SVA_TRANS,
530 pci_err(qm->pdev, "failed to close sva prefetch\n");
533 static void hisi_zip_enable_clock_gate(struct hisi_qm *qm)
537 if (qm->ver < QM_HW_V3)
540 val = readl(qm->io_base + HZIP_CLOCK_GATE_CTRL);
542 writel(val, qm->io_base + HZIP_CLOCK_GATE_CTRL);
544 val = readl(qm->io_base + HZIP_PEH_CFG_AUTO_GATE);
546 writel(val, qm->io_base + HZIP_PEH_CFG_AUTO_GATE);
549 static int hisi_zip_set_user_domain_and_cache(struct hisi_qm *qm)
551 void __iomem *base = qm->io_base;
554 /* qm user domain */
561 /* qm cache */
579 if (qm->use_sva && qm->ver == QM_HW_V2) {
590 dcomp_bm = qm->cap_tables.dev_cap_table[ZIP_DECOMP_ENABLE_BITMAP_IDX].cap_val;
591 comp_bm = qm->cap_tables.dev_cap_table[ZIP_COMP_ENABLE_BITMAP_IDX].cap_val;
599 hisi_zip_enable_clock_gate(qm);
604 static void hisi_zip_master_ooo_ctrl(struct hisi_qm *qm, bool enable)
608 val1 = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
611 val2 = hisi_qm_get_hw_info(qm, zip_basic_cap_info,
612 ZIP_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver);
618 if (qm->ver > QM_HW_V2)
619 writel(val2, qm->io_base + HZIP_OOO_SHUTDOWN_SEL);
621 writel(val1, qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
624 static void hisi_zip_hw_error_enable(struct hisi_qm *qm)
628 if (qm->ver == QM_HW_V1) {
630 qm->io_base + HZIP_CORE_INT_MASK_REG);
631 dev_info(&qm->pdev->dev, "Does not support hw error handle\n");
635 nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver);
636 ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CE_MASK_CAP, qm->cap_ver);
639 writel(ce | nfe | HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_SOURCE);
642 writel(ce, qm->io_base + HZIP_CORE_INT_RAS_CE_ENB);
643 writel(HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_RAS_FE_ENB);
644 writel(nfe, qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);
646 hisi_zip_master_ooo_ctrl(qm, true);
649 writel(0, qm->io_base + HZIP_CORE_INT_MASK_REG);
652 static void hisi_zip_hw_error_disable(struct hisi_qm *qm)
657 nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver);
658 ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CE_MASK_CAP, qm->cap_ver);
659 writel(ce | nfe | HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_MASK_REG);
661 hisi_zip_master_ooo_ctrl(qm, false);
668 return &hisi_zip->qm;
671 static u32 clear_enable_read(struct hisi_qm *qm)
673 return readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) &
677 static int clear_enable_write(struct hisi_qm *qm, u32 val)
684 tmp = (readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) &
686 writel(tmp, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE);
695 struct hisi_qm *qm = file_to_qm(file);
700 ret = hisi_qm_get_dfx_access(qm);
707 val = clear_enable_read(qm);
714 hisi_qm_put_dfx_access(qm);
720 hisi_qm_put_dfx_access(qm);
729 struct hisi_qm *qm = file_to_qm(file);
749 ret = hisi_qm_get_dfx_access(qm);
756 ret = clear_enable_write(qm, val);
769 hisi_qm_put_dfx_access(qm);
809 static int hisi_zip_core_debug_init(struct hisi_qm *qm)
812 struct device *dev = &qm->pdev->dev;
818 zip_core_num = qm->cap_tables.dev_cap_table[ZIP_CORE_NUM_CAP_IDX].cap_val;
819 zip_comp_core_num = qm->cap_tables.dev_cap_table[ZIP_CLUSTER_COMP_NUM_CAP_IDX].cap_val;
834 regset->base = qm->io_base + core_offsets[i];
837 tmp_d = debugfs_create_dir(buf, qm->debug.debug_root);
845 static void hisi_zip_dfx_debug_init(struct hisi_qm *qm)
847 struct dfx_diff_registers *hzip_regs = qm->debug.acc_diff_regs;
848 struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm);
854 tmp_dir = debugfs_create_dir("zip_dfx", qm->debug.debug_root);
862 if (qm->fun_type == QM_HW_PF && hzip_regs)
864 qm, &hzip_diff_regs_fops);
867 static int hisi_zip_ctrl_debug_init(struct hisi_qm *qm)
869 struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm);
878 qm->debug.debug_root,
883 return hisi_zip_core_debug_init(qm);
886 static int hisi_zip_debugfs_init(struct hisi_qm *qm)
888 struct device *dev = &qm->pdev->dev;
894 qm->debug.sqe_mask_offset = HZIP_SQE_MASK_OFFSET;
895 qm->debug.sqe_mask_len = HZIP_SQE_MASK_LEN;
896 qm->debug.debug_root = dev_d;
897 ret = hisi_qm_regs_debugfs_init(qm, hzip_diff_regs, ARRAY_SIZE(hzip_diff_regs));
903 hisi_qm_debug_init(qm);
905 if (qm->fun_type == QM_HW_PF) {
906 ret = hisi_zip_ctrl_debug_init(qm);
911 hisi_zip_dfx_debug_init(qm);
916 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hzip_diff_regs));
923 static void hisi_zip_debug_regs_clear(struct hisi_qm *qm)
928 writel(HZIP_RD_CNT_CLR_CE_EN, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE);
931 readl(qm->io_base + core_offsets[i] +
935 writel(0x0, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE);
937 hisi_qm_debug_regs_clear(qm);
940 static void hisi_zip_debugfs_exit(struct hisi_qm *qm)
942 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hzip_diff_regs));
944 debugfs_remove_recursive(qm->debug.debug_root);
946 if (qm->fun_type == QM_HW_PF) {
947 hisi_zip_debug_regs_clear(qm);
948 qm->debug.curr_qm_qp_num = 0;
952 static int hisi_zip_show_last_regs_init(struct hisi_qm *qm)
956 struct qm_debug *debug = &qm->debug;
961 zip_core_num = qm->cap_tables.dev_cap_table[ZIP_CORE_NUM_CAP_IDX].cap_val;
969 io_base = qm->io_base + hzip_com_dfx_regs[i].offset;
974 io_base = qm->io_base + core_offsets[i];
985 static void hisi_zip_show_last_regs_uninit(struct hisi_qm *qm)
987 struct qm_debug *debug = &qm->debug;
989 if (qm->fun_type == QM_HW_VF || !debug->last_words)
996 static void hisi_zip_show_last_dfx_regs(struct hisi_qm *qm)
1001 struct qm_debug *debug = &qm->debug;
1007 if (qm->fun_type == QM_HW_VF || !debug->last_words)
1011 val = readl_relaxed(qm->io_base + hzip_com_dfx_regs[i].offset);
1013 pci_info(qm->pdev, "com_dfx: %s \t= 0x%08x => 0x%08x\n",
1017 zip_core_num = qm->cap_tables.dev_cap_table[ZIP_CORE_NUM_CAP_IDX].cap_val;
1018 zip_comp_core_num = qm->cap_tables.dev_cap_table[ZIP_CLUSTER_COMP_NUM_CAP_IDX].cap_val;
1026 base = qm->io_base + core_offsets[i];
1028 pci_info(qm->pdev, "==>%s:\n", buf);
1034 pci_info(qm->pdev, "%s \t= 0x%08x => 0x%08x\n",
1041 static void hisi_zip_log_hw_error(struct hisi_qm *qm, u32 err_sts)
1044 struct device *dev = &qm->pdev->dev;
1053 err_val = readl(qm->io_base +
1064 static u32 hisi_zip_get_hw_err_status(struct hisi_qm *qm)
1066 return readl(qm->io_base + HZIP_CORE_INT_STATUS);
1069 static void hisi_zip_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts)
1073 writel(err_sts, qm->io_base + HZIP_CORE_INT_SOURCE);
1074 nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver);
1075 writel(nfe, qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);
1078 static void hisi_zip_open_axi_master_ooo(struct hisi_qm *qm)
1082 val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
1085 qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
1088 qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
1091 static void hisi_zip_close_axi_master_ooo(struct hisi_qm *qm)
1096 nfe_enb = readl(qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);
1098 qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);
1102 qm->io_base + HZIP_CORE_INT_SET);
1105 static void hisi_zip_err_info_init(struct hisi_qm *qm)
1107 struct hisi_qm_err_info *err_info = &qm->err_info;
1110 err_info->ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_QM_CE_MASK_CAP, qm->cap_ver);
1111 err_info->nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info,
1112 ZIP_QM_NFE_MASK_CAP, qm->cap_ver);
1114 err_info->qm_shutdown_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info,
1115 ZIP_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver);
1116 err_info->dev_shutdown_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info,
1117 ZIP_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver);
1118 err_info->qm_reset_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info,
1119 ZIP_QM_RESET_MASK_CAP, qm->cap_ver);
1120 err_info->dev_reset_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info,
1121 ZIP_RESET_MASK_CAP, qm->cap_ver);
1143 struct hisi_qm *qm = &hisi_zip->qm;
1147 ctrl = devm_kzalloc(&qm->pdev->dev, sizeof(*ctrl), GFP_KERNEL);
1153 qm->err_ini = &hisi_zip_err_ini;
1154 qm->err_ini->err_info_init(qm);
1156 ret = hisi_zip_set_user_domain_and_cache(qm);
1160 ret = hisi_zip_set_high_perf(qm);
1164 hisi_zip_open_sva_prefetch(qm);
1165 hisi_qm_dev_err_init(qm);
1166 hisi_zip_debug_regs_clear(qm);
1168 ret = hisi_zip_show_last_regs_init(qm);
1170 pci_err(qm->pdev, "Failed to init last word regs!\n");
1175 static int zip_pre_store_cap_reg(struct hisi_qm *qm)
1178 struct pci_dev *pdev = qm->pdev;
1188 zip_cap[i].cap_val = hisi_qm_get_hw_info(qm, zip_basic_cap_info,
1189 zip_pre_store_caps[i], qm->cap_ver);
1192 qm->cap_tables.dev_cap_table = zip_cap;
1197 static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
1202 qm->pdev = pdev;
1203 qm->ver = pdev->revision;
1204 qm->mode = uacce_mode;
1205 qm->sqe_size = HZIP_SQE_SIZE;
1206 qm->dev_name = hisi_zip_name;
1208 qm->fun_type = (pdev->device == PCI_DEVICE_ID_HUAWEI_ZIP_PF) ?
1210 if (qm->fun_type == QM_HW_PF) {
1211 qm->qp_base = HZIP_PF_DEF_Q_BASE;
1212 qm->qp_num = pf_q_num;
1213 qm->debug.curr_qm_qp_num = pf_q_num;
1214 qm->qm_list = &zip_devices;
1216 set_bit(QM_MODULE_PARAM, &qm->misc_ctl);
1217 } else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) {
1219 * have no way to get qm configure in VM in v1 hardware,
1225 qm->qp_base = HZIP_PF_DEF_Q_NUM;
1226 qm->qp_num = HZIP_QUEUE_NUM_V1 - HZIP_PF_DEF_Q_NUM;
1229 ret = hisi_qm_init(qm);
1231 pci_err(qm->pdev, "Failed to init zip qm configures!\n");
1236 ret = zip_pre_store_cap_reg(qm);
1238 pci_err(qm->pdev, "Failed to pre-store capability registers!\n");
1239 hisi_qm_uninit(qm);
1243 alg_msk = qm->cap_tables.dev_cap_table[ZIP_DEV_ALG_BITMAP_IDX].cap_val;
1244 ret = hisi_qm_set_algs(qm, alg_msk, zip_dev_algs, ARRAY_SIZE(zip_dev_algs));
1246 pci_err(qm->pdev, "Failed to set zip algs!\n");
1247 hisi_qm_uninit(qm);
1253 static void hisi_zip_qm_uninit(struct hisi_qm *qm)
1255 hisi_qm_uninit(qm);
1261 struct hisi_qm *qm = &hisi_zip->qm;
1264 if (qm->fun_type == QM_HW_PF) {
1269 if (qm->ver >= QM_HW_V3) {
1274 qm->type_rate = type_rate;
1284 struct hisi_qm *qm;
1291 qm = &hisi_zip->qm;
1293 ret = hisi_zip_qm_init(qm, pdev);
1305 ret = hisi_qm_start(qm);
1309 ret = hisi_zip_debugfs_init(qm);
1313 ret = hisi_qm_alg_register(qm, &zip_devices);
1319 if (qm->uacce) {
1320 ret = uacce_register(qm->uacce);
1327 if (qm->fun_type == QM_HW_PF && vfs_num > 0) {
1333 hisi_qm_pm_init(qm);
1338 hisi_qm_alg_unregister(qm, &zip_devices);
1341 hisi_zip_debugfs_exit(qm);
1342 hisi_qm_stop(qm, QM_NORMAL);
1345 hisi_zip_show_last_regs_uninit(qm);
1346 hisi_qm_dev_err_uninit(qm);
1349 hisi_zip_qm_uninit(qm);
1356 struct hisi_qm *qm = pci_get_drvdata(pdev);
1358 hisi_qm_pm_uninit(qm);
1359 hisi_qm_wait_task_finish(qm, &zip_devices);
1360 hisi_qm_alg_unregister(qm, &zip_devices);
1362 if (qm->fun_type == QM_HW_PF && qm->vfs_num)
1365 hisi_zip_debugfs_exit(qm);
1366 hisi_qm_stop(qm, QM_NORMAL);
1367 hisi_zip_show_last_regs_uninit(qm);
1368 hisi_qm_dev_err_uninit(qm);
1369 hisi_zip_qm_uninit(qm);