Lines Matching defs:base
551 void __iomem *base = qm->io_base;
555 writel(AXUSER_BASE, base + QM_ARUSER_M_CFG_1);
556 writel(ARUSER_M_CFG_ENABLE, base + QM_ARUSER_M_CFG_ENABLE);
557 writel(AXUSER_BASE, base + QM_AWUSER_M_CFG_1);
558 writel(AWUSER_M_CFG_ENABLE, base + QM_AWUSER_M_CFG_ENABLE);
559 writel(WUSER_M_CFG_ENABLE, base + QM_WUSER_M_CFG_ENABLE);
562 writel(AXI_M_CFG, base + QM_AXI_M_CFG);
563 writel(AXI_M_CFG_ENABLE, base + QM_AXI_M_CFG_ENABLE);
566 writel(PEH_AXUSER_CFG, base + QM_PEH_AXUSER_CFG);
567 writel(PEH_AXUSER_CFG_ENABLE, base + QM_PEH_AXUSER_CFG_ENABLE);
570 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_0);
571 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_1);
572 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_0);
573 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_1);
576 writel(AXUSER_BASE, base + HZIP_BD_RUSER_32_63);
577 writel(AXUSER_BASE, base + HZIP_BD_WUSER_32_63);
580 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_RUSER_32_63);
581 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_WUSER_32_63);
582 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_SGL_RUSER_32_63);
584 writel(AXUSER_BASE, base + HZIP_DATA_RUSER_32_63);
585 writel(AXUSER_BASE, base + HZIP_DATA_WUSER_32_63);
586 writel(AXUSER_BASE, base + HZIP_SGL_RUSER_32_63);
592 writel(HZIP_DECOMP_CHECK_ENABLE | dcomp_bm | comp_bm, base + HZIP_CLOCK_GATE_CTRL);
597 FIELD_PREP(CQC_CACHE_WB_THRD, 1), base + QM_CACHE_CTL);
834 regset->base = qm->io_base + core_offsets[i];
1003 void __iomem *base;
1026 base = qm->io_base + core_offsets[i];
1032 val = readl_relaxed(base + hzip_dump_dfx_regs[j].offset);