Lines Matching refs:val
435 u32 val;
551 u32 val, dev_val;
556 val = qm_get_hw_error_status(qm) & qm->err_info.qm_shutdown_mask;
559 return val || dev_val;
617 u32 val;
620 val, !((val >> QM_MB_BUSY_SHIFT) &
655 u32 val;
671 val = readl(qm->io_base + QM_MB_CMD_SEND_BASE);
672 if (val & QM_MB_STATUS_MASK) {
745 u32 val;
751 val = readl(qm->io_base + QM_PM_CTRL);
752 val |= QM_IDLE_DISABLE;
753 writel(val, qm->io_base + QM_PM_CTRL);
758 u32 val;
761 return readl_relaxed_poll_timeout(qm->io_base + QM_MEM_INIT_DONE, val,
762 val & BIT(0), POLL_PERIOD,
779 u32 val;
790 val = readl(qm->io_base + info_table[index].offset);
791 return (val >> info_table[index].shift) & info_table[index].mask;
986 u32 val;
988 val = readl(qm->io_base + QM_IFC_INT_STATUS);
989 val &= QM_IFC_INT_STATUS_MASK;
990 if (!val)
1160 return shaper_cbs_s[i].val;
1173 return shaper_cir_s[i].val;
1254 unsigned int val;
1260 ret = readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
1261 val & BIT(0), POLL_PERIOD,
1278 return readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
1279 val & BIT(0), POLL_PERIOD,
1316 /* init default shaper qos val */
1533 u32 val;
1538 val = readl(qm->io_base + QM_IFC_INT_SOURCE_V);
1539 val |= QM_IFC_INT_SOURCE_MASK;
1540 writel(val, qm->io_base + QM_IFC_INT_SOURCE_V);
1579 u64 val;
1586 val = readq(qm->io_base + QM_IFC_INT_SOURCE_P);
1588 if ((val & GENMASK(vfs_num, 1)) == GENMASK(vfs_num, 1))
1601 if (val & BIT(i))
1608 qm_clear_cmd_interrupt(qm, val);
1615 u32 val;
1617 val = readl(qm->io_base + QM_IFC_INT_CFG);
1618 val &= ~QM_IFC_SEND_ALL_VFS;
1619 val |= fun_num;
1620 writel(val, qm->io_base + QM_IFC_INT_CFG);
1622 val = readl(qm->io_base + QM_IFC_INT_SET_P);
1623 val |= QM_IFC_INT_SET_MASK;
1624 writel(val, qm->io_base + QM_IFC_INT_SET_P);
1629 u32 val;
1631 val = readl(qm->io_base + QM_IFC_INT_SET_V);
1632 val |= QM_IFC_INT_SET_MASK;
1633 writel(val, qm->io_base + QM_IFC_INT_SET_V);
1641 u64 val;
1655 val = readq(qm->io_base + QM_IFC_READY_STATUS);
1657 if (!(val & BIT(fun_num)))
1677 u64 val = 0;
1695 val = readq(qm->io_base + QM_IFC_READY_STATUS);
1697 if (!(val & GENMASK(vfs_num, 1))) {
1710 if (val & BIT(i))
1721 u32 val;
1736 val = readl(qm->io_base + QM_IFC_INT_SET_V);
1737 if (!(val & QM_IFC_INT_STATUS_MASK))
1783 u32 val;
1801 val, !(val & QM_PEH_DFX_MASK),
1807 val, !(val & QM_PEH_MSI_FINISH_MASK),
2305 unsigned int val;
2312 val, val & BIT(0), POLL_PERIOD,
2860 u32 val;
2865 val = readl(qm->io_base + QM_IFC_INT_MASK);
2866 val |= QM_IFC_INT_DISABLE;
2867 writel(val, qm->io_base + QM_IFC_INT_MASK);
2872 u32 val;
2881 val = readl(qm->io_base + QM_IFC_INT_MASK);
2882 val &= ~QM_IFC_INT_DISABLE;
2883 writel(val, qm->io_base + QM_IFC_INT_MASK);
3594 unsigned int val;
3598 ret = readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
3599 val & BIT(0), POLL_PERIOD,
3611 ret = readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
3612 val & BIT(0), POLL_PERIOD,
3664 /* reset mailbox qos val */
3729 unsigned long *val,
3743 ret = kstrtoul(val_buf, 10, val);
3744 if (ret || *val == 0 || *val > QM_QOS_MAX_VAL) {
3768 unsigned long val;
3782 ret = qm_get_qos_value(qm, tbuf, &val, &fun_index);
3798 ret = qm_func_shaper_enable(qm, fun_index, val);
3806 fun_index, val);
4036 u32 val;
4042 ret = readl_relaxed_poll_timeout(qm->io_base + QM_PEH_VENDOR_ID, val,
4043 (val == ACC_VENDOR_ID_VALUE),
4051 ret = readl_relaxed_poll_timeout(qm->io_base + QM_PEH_VENDOR_ID, val,
4052 (val == PCI_VENDOR_ID_HUAWEI),
4231 u32 val;
4260 val,
4261 (val == ACC_MASTER_TRANS_RETURN_RW),
4764 u32 val, cmd;
4769 ret = readl_relaxed_poll_timeout(qm->io_base + QM_IFC_INT_SOURCE_V, val,
4770 val == BIT(0), QM_VF_RESET_WAIT_US,
4868 u64 val;
4872 val = readq(qm->io_base + QM_IFC_INT_SOURCE_P);
4873 if (!val)
4877 if (val & BIT(i))
4951 u32 irq_vector, val;
4956 val = qm->cap_tables.qm_cap_table[QM_ABN_IRQ_TYPE_CAP_IDX].cap_val;
4957 if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_ABN_IRQ_TYPE_MASK))
4960 irq_vector = val & QM_IRQ_VECTOR_MASK;
4967 u32 irq_vector, val;
4973 val = qm->cap_tables.qm_cap_table[QM_ABN_IRQ_TYPE_CAP_IDX].cap_val;
4974 if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_ABN_IRQ_TYPE_MASK))
4977 irq_vector = val & QM_IRQ_VECTOR_MASK;
4988 u32 irq_vector, val;
4990 val = qm->cap_tables.qm_cap_table[QM_PF2VF_IRQ_TYPE_CAP_IDX].cap_val;
4991 if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK))
4994 irq_vector = val & QM_IRQ_VECTOR_MASK;
5001 u32 irq_vector, val;
5004 val = qm->cap_tables.qm_cap_table[QM_PF2VF_IRQ_TYPE_CAP_IDX].cap_val;
5005 if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK))
5008 irq_vector = val & QM_IRQ_VECTOR_MASK;
5019 u32 irq_vector, val;
5021 val = qm->cap_tables.qm_cap_table[QM_AEQ_IRQ_TYPE_CAP_IDX].cap_val;
5022 if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK))
5025 irq_vector = val & QM_IRQ_VECTOR_MASK;
5032 u32 irq_vector, val;
5035 val = qm->cap_tables.qm_cap_table[QM_AEQ_IRQ_TYPE_CAP_IDX].cap_val;
5036 if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK))
5039 irq_vector = val & QM_IRQ_VECTOR_MASK;
5051 u32 irq_vector, val;
5053 val = qm->cap_tables.qm_cap_table[QM_EQ_IRQ_TYPE_CAP_IDX].cap_val;
5054 if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK))
5057 irq_vector = val & QM_IRQ_VECTOR_MASK;
5064 u32 irq_vector, val;
5067 val = qm->cap_tables.qm_cap_table[QM_EQ_IRQ_TYPE_CAP_IDX].cap_val;
5068 if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK))
5071 irq_vector = val & QM_IRQ_VECTOR_MASK;
5183 u32 val, i;
5186 val = hisi_qm_get_hw_info(qm, qm_cap_info_comm, QM_SUPPORT_DB_ISOLATION, true);
5187 if (val)
5191 val = readl(qm->io_base + QM_FUNC_CAPS_REG);
5192 qm->cap_ver = val & QM_CAPBILITY_VERSION;
5197 val = hisi_qm_get_hw_info(qm, qm_cap_info_comm, i, qm->cap_ver);
5198 if (val)
5204 val = hisi_qm_get_hw_info(qm, cap_info, i, qm->cap_ver);
5205 if (val)
5563 u32 val;
5576 val,
5577 (val == ACC_MASTER_TRANS_RETURN_RW),