Lines Matching defs:io_base
540 return readl(qm->io_base + QM_ABNORMAL_INT_STATUS);
619 return readl_relaxed_poll_timeout(qm->io_base + QM_MB_CMD_SEND_BASE,
628 void __iomem *fun_base = qm->io_base + QM_MB_CMD_SEND_BASE;
671 val = readl(qm->io_base + QM_MB_CMD_SEND_BASE);
712 writeq(doorbell, qm->io_base + QM_DOORBELL_BASE_V1);
717 void __iomem *io_base = qm->io_base;
722 io_base = qm->db_io_base + (u64)qn * qm->db_interval +
725 io_base += QM_DOORBELL_EQ_AEQ_BASE_V2;
732 writeq(doorbell, io_base);
751 val = readl(qm->io_base + QM_PM_CTRL);
753 writel(val, qm->io_base + QM_PM_CTRL);
760 writel(0x1, qm->io_base + QM_MEM_START_INIT);
761 return readl_relaxed_poll_timeout(qm->io_base + QM_MEM_INIT_DONE, val,
790 val = readl(qm->io_base + info_table[index].offset);
988 val = readl(qm->io_base + QM_IFC_INT_STATUS);
1134 writel(page_type, qm->io_base + QM_PAGE_SIZE);
1246 writel(lower_32_bits(tmp), qm->io_base + QM_VFT_CFG_DATA_L);
1247 writel(upper_32_bits(tmp), qm->io_base + QM_VFT_CFG_DATA_H);
1260 ret = readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
1266 writel(0x0, qm->io_base + QM_VFT_CFG_OP_WR);
1267 writel(type, qm->io_base + QM_VFT_CFG_TYPE);
1271 writel(fun_num, qm->io_base + QM_VFT_CFG);
1275 writel(0x0, qm->io_base + QM_VFT_CFG_RDY);
1276 writel(0x1, qm->io_base + QM_VFT_CFG_OP_ENABLE);
1278 return readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
1293 writel(qm->type_rate, qm->io_base + QM_SHAPER_CFG);
1340 sqc_vft = readl(qm->io_base + QM_MB_CMD_DATA_ADDR_L) |
1341 ((u64)readl(qm->io_base + QM_MB_CMD_DATA_ADDR_H) << 32);
1390 writel(QM_ABNORMAL_INT_MASK_VALUE, qm->io_base + QM_ABNORMAL_INT_MASK);
1399 writel(qm->error_mask, qm->io_base + QM_ABNORMAL_INT_SOURCE);
1402 writel(err_info->ce, qm->io_base + QM_RAS_CE_ENABLE);
1403 writel(QM_RAS_CE_TIMES_PER_IRQ, qm->io_base + QM_RAS_CE_THRESHOLD);
1404 writel(err_info->nfe, qm->io_base + QM_RAS_NFE_ENABLE);
1405 writel(err_info->fe, qm->io_base + QM_RAS_FE_ENABLE);
1415 irq_unmask &= readl(qm->io_base + QM_ABNORMAL_INT_MASK);
1416 writel(irq_unmask, qm->io_base + QM_ABNORMAL_INT_MASK);
1423 irq_mask |= readl(qm->io_base + QM_ABNORMAL_INT_MASK);
1424 writel(irq_mask, qm->io_base + QM_ABNORMAL_INT_MASK);
1434 writel(qm->err_info.qm_shutdown_mask, qm->io_base + QM_OOO_SHUTDOWN_SEL);
1437 irq_unmask &= readl(qm->io_base + QM_ABNORMAL_INT_MASK);
1438 writel(irq_unmask, qm->io_base + QM_ABNORMAL_INT_MASK);
1445 irq_mask |= readl(qm->io_base + QM_ABNORMAL_INT_MASK);
1446 writel(irq_mask, qm->io_base + QM_ABNORMAL_INT_MASK);
1449 writel(0x0, qm->io_base + QM_OOO_SHUTDOWN_SEL);
1468 reg_val = readl(qm->io_base + QM_ABNORMAL_INF01);
1475 reg_val = readl(qm->io_base + QM_ABNORMAL_INF00);
1494 tmp = readl(qm->io_base + QM_ABNORMAL_INT_STATUS);
1505 writel(error_status, qm->io_base + QM_ABNORMAL_INT_SOURCE);
1506 writel(qm->err_info.nfe, qm->io_base + QM_RAS_NFE_ENABLE);
1523 *msg = readl(qm->io_base + QM_MB_CMD_DATA_ADDR_L) |
1524 ((u64)readl(qm->io_base + QM_MB_CMD_DATA_ADDR_H) << 32);
1536 writeq(vf_mask, qm->io_base + QM_IFC_INT_SOURCE_P);
1538 val = readl(qm->io_base + QM_IFC_INT_SOURCE_V);
1540 writel(val, qm->io_base + QM_IFC_INT_SOURCE_V);
1586 val = readq(qm->io_base + QM_IFC_INT_SOURCE_P);
1617 val = readl(qm->io_base + QM_IFC_INT_CFG);
1620 writel(val, qm->io_base + QM_IFC_INT_CFG);
1622 val = readl(qm->io_base + QM_IFC_INT_SET_P);
1624 writel(val, qm->io_base + QM_IFC_INT_SET_P);
1631 val = readl(qm->io_base + QM_IFC_INT_SET_V);
1633 writel(val, qm->io_base + QM_IFC_INT_SET_V);
1655 val = readq(qm->io_base + QM_IFC_READY_STATUS);
1695 val = readq(qm->io_base + QM_IFC_READY_STATUS);
1736 val = readl(qm->io_base + QM_IFC_INT_SET_V);
1771 if (readl(qm->io_base + QM_PEH_DFX_INFO0))
1800 ret = readl_relaxed_poll_timeout(qm->io_base + QM_PEH_DFX_INFO0,
1806 ret = readl_relaxed_poll_timeout(qm->io_base + QM_PEH_DFX_INFO1,
2310 writel(0x1, qm->io_base + QM_CACHE_WB_START);
2311 if (readl_relaxed_poll_timeout(qm->io_base + QM_CACHE_WB_DONE,
2865 val = readl(qm->io_base + QM_IFC_INT_MASK);
2867 writel(val, qm->io_base + QM_IFC_INT_MASK);
2881 val = readl(qm->io_base + QM_IFC_INT_MASK);
2883 writel(val, qm->io_base + QM_IFC_INT_MASK);
2893 iounmap(qm->io_base);
2909 writel(state, qm->io_base + QM_VF_STATE);
3031 writel(0x0, qm->io_base + QM_VF_EQ_INT_MASK);
3032 writel(0x0, qm->io_base + QM_VF_AEQ_INT_MASK);
3037 writel(0x1, qm->io_base + QM_VF_EQ_INT_MASK);
3038 writel(0x1, qm->io_base + QM_VF_AEQ_INT_MASK);
3598 ret = readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
3604 writel(0x1, qm->io_base + QM_VFT_CFG_OP_WR);
3605 writel(SHAPER_VFT, qm->io_base + QM_VFT_CFG_TYPE);
3606 writel(fun_index, qm->io_base + QM_VFT_CFG);
3608 writel(0x0, qm->io_base + QM_VFT_CFG_RDY);
3609 writel(0x1, qm->io_base + QM_VFT_CFG_OP_ENABLE);
3611 ret = readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
3617 shaper_vft = readl(qm->io_base + QM_VFT_CFG_DATA_L) |
3618 ((u64)readl(qm->io_base + QM_VFT_CFG_DATA_H) << 32);
4041 writel(ACC_VENDOR_ID_VALUE, qm->io_base + QM_PEH_VENDOR_ID);
4042 ret = readl_relaxed_poll_timeout(qm->io_base + QM_PEH_VENDOR_ID, val,
4050 writel(PCI_VENDOR_ID_HUAWEI, qm->io_base + QM_PEH_VENDOR_ID);
4051 ret = readl_relaxed_poll_timeout(qm->io_base + QM_PEH_VENDOR_ID, val,
4220 nfe_enb = readl(qm->io_base + QM_RAS_NFE_ENABLE);
4222 qm->io_base + QM_RAS_NFE_ENABLE);
4223 writel(QM_ECC_MBIT, qm->io_base + QM_ABNORMAL_INT_SET);
4256 qm->io_base + ACC_MASTER_GLOBAL_CTRL);
4259 ret = readl_relaxed_poll_timeout(qm->io_base + ACC_MASTER_TRANS_RETURN,
4379 value = readl(qm->io_base + ACC_AM_CFG_PORT_WR_EN);
4381 qm->io_base + ACC_AM_CFG_PORT_WR_EN);
4389 writel(QM_ECC_MBIT, qm->io_base + QM_ABNORMAL_INT_SOURCE);
4392 writel(ACC_ROB_ECC_ERR_MULTPL, qm->io_base + ACC_AM_ROB_ECC_INT_STS);
4407 value = readl(qm->io_base + ACC_AM_CFG_PORT_WR_EN);
4409 writel(value, qm->io_base + ACC_AM_CFG_PORT_WR_EN);
4769 ret = readl_relaxed_poll_timeout(qm->io_base + QM_IFC_INT_SOURCE_V, val,
4872 val = readq(qm->io_base + QM_IFC_INT_SOURCE_P);
5191 val = readl(qm->io_base + QM_FUNC_CAPS_REG);
5226 qm->io_base = ioremap(qm->phys_base, pci_resource_len(pdev, PCI_BAR_2));
5227 if (!qm->io_base) {
5247 qm->db_io_base = qm->io_base;
5261 iounmap(qm->io_base);
5448 writel(QM_DB_TIMEOUT_SET, qm->io_base + QM_DB_TIMEOUT_CFG);
5573 qm->io_base + ACC_MASTER_GLOBAL_CTRL);
5575 ret = readl_relaxed_poll_timeout(qm->io_base + ACC_MASTER_TRANS_RETURN,
5617 writel(QM_DB_TIMEOUT_SET, qm->io_base + QM_DB_TIMEOUT_CFG);