Lines Matching refs:val
105 u32 cache_params, ace_const, val;
113 val = drvdata->coherent ? 0xb : 0x2;
117 cache_params |= FIELD_PREP(mask, val);
121 cache_params |= FIELD_PREP(mask, val);
125 cache_params |= FIELD_PREP(mask, val);
139 val = drvdata->coherent ? 0x2 : 0x3;
143 ace_const |= FIELD_PREP(mask, val);
147 ace_const |= FIELD_PREP(mask, val);
159 __le32 val;
165 return le32_to_cpu(idr.val);
249 unsigned int val;
260 val = cc_ioread(drvdata, CC_REG(NVM_IS_IDLE));
261 if (val & CC_NVM_IS_IDLE_MASK) {
274 unsigned int val;
280 val = cc_ioread(drvdata, CC_REG(AXIM_CFG));
281 cc_iowrite(drvdata, CC_REG(AXIM_CFG), val & ~CC_AXI_IRQ_MASK);
287 val = cc_ioread(drvdata, CC_REG(HOST_IRR));
288 dev_dbg(dev, "IRR=0x%08X\n", val);
289 cc_iowrite(drvdata, CC_REG(HOST_ICR), val);
292 val = drvdata->comp_mask | CC_AXI_ERR_IRQ_MASK;
295 val |= CC_GPR0_IRQ_MASK;
297 cc_iowrite(drvdata, CC_REG(HOST_IMR), ~val);
312 u32 val, hw_rev_pidr, sig_cidr;
406 val = cc_ioread(new_drvdata, new_drvdata->sig_offset);
407 if (val != hw_rev->sig) {
409 val, hw_rev->sig);
413 sig_cidr = val;
417 val = cc_read_idr(new_drvdata, pidr_0124_offsets);
418 if (val != hw_rev->pidr_0124) {
420 val, hw_rev->pidr_0124);
424 hw_rev_pidr = val;
426 val = cc_read_idr(new_drvdata, cidr_0123_offsets);
427 if (val != hw_rev->cidr_0123) {
429 val, hw_rev->cidr_0123);
433 sig_cidr = val;
436 val = cc_ioread(new_drvdata, CC_REG(HOST_REMOVE_INPUT_PINS));
437 switch (val) {
454 val = cc_ioread(new_drvdata, CC_REG(SECURITY_DISABLED));
455 val &= CC_SECURITY_DISABLED_MASK;
456 new_drvdata->sec_disabled |= !!val;