Lines Matching defs:new_drvdata
309 struct cc_drvdata *new_drvdata;
319 new_drvdata = devm_kzalloc(dev, sizeof(*new_drvdata), GFP_KERNEL);
320 if (!new_drvdata)
324 new_drvdata->hw_rev_name = hw_rev->name;
325 new_drvdata->hw_rev = hw_rev->rev;
326 new_drvdata->std_bodies = hw_rev->std_bodies;
329 new_drvdata->axim_mon_offset = CC_REG(AXIM_MON_COMP);
330 new_drvdata->sig_offset = CC_REG(HOST_SIGNATURE_712);
331 new_drvdata->ver_offset = CC_REG(HOST_VERSION_712);
333 new_drvdata->axim_mon_offset = CC_REG(AXIM_MON_COMP8);
334 new_drvdata->sig_offset = CC_REG(HOST_SIGNATURE_630);
335 new_drvdata->ver_offset = CC_REG(HOST_VERSION_630);
338 new_drvdata->comp_mask = CC_COMP_IRQ_MASK;
340 platform_set_drvdata(plat_dev, new_drvdata);
341 new_drvdata->plat_dev = plat_dev;
346 new_drvdata->clk = clk;
348 new_drvdata->coherent = of_dma_is_coherent(np);
353 new_drvdata->cc_base = devm_platform_get_and_ioremap_resource(plat_dev,
355 if (IS_ERR(new_drvdata->cc_base))
356 return PTR_ERR(new_drvdata->cc_base);
361 &req_mem_cc_regs->start, new_drvdata->cc_base);
368 init_completion(&new_drvdata->hw_queue_avail);
381 rc = clk_prepare_enable(new_drvdata->clk);
387 new_drvdata->sec_disabled = cc_sec_disable;
400 if (!cc_wait_for_reset_completion(new_drvdata)) {
406 val = cc_ioread(new_drvdata, new_drvdata->sig_offset);
414 hw_rev_pidr = cc_ioread(new_drvdata, new_drvdata->ver_offset);
417 val = cc_read_idr(new_drvdata, pidr_0124_offsets);
426 val = cc_read_idr(new_drvdata, cidr_0123_offsets);
436 val = cc_ioread(new_drvdata, CC_REG(HOST_REMOVE_INPUT_PINS));
442 if (new_drvdata->std_bodies & CC_STD_NIST) {
444 new_drvdata->std_bodies = CC_STD_OSCCA;
454 val = cc_ioread(new_drvdata, CC_REG(SECURITY_DISABLED));
456 new_drvdata->sec_disabled |= !!val;
458 if (!new_drvdata->sec_disabled) {
459 new_drvdata->comp_mask |= CC_CPP_SM4_ABORT_MASK;
460 if (new_drvdata->std_bodies & CC_STD_NIST)
461 new_drvdata->comp_mask |= CC_CPP_AES_ABORT_MASK;
465 if (new_drvdata->sec_disabled)
473 new_drvdata);
480 init_cc_cache_params(new_drvdata);
482 rc = init_cc_regs(new_drvdata);
488 rc = cc_debugfs_init(new_drvdata);
494 rc = cc_fips_init(new_drvdata);
499 rc = cc_sram_mgr_init(new_drvdata);
505 new_drvdata->mlli_sram_addr =
506 cc_sram_alloc(new_drvdata, MAX_MLLI_BUFF_SIZE);
507 if (new_drvdata->mlli_sram_addr == NULL_SRAM_ADDR) {
512 rc = cc_req_mgr_init(new_drvdata);
518 rc = cc_buffer_mgr_init(new_drvdata);
527 rc = cc_hash_alloc(new_drvdata);
534 rc = cc_cipher_alloc(new_drvdata);
540 rc = cc_aead_alloc(new_drvdata);
550 cc_set_ree_fips_status(new_drvdata, true);
556 cc_cipher_free(new_drvdata);
558 cc_hash_free(new_drvdata);
560 cc_buffer_mgr_fini(new_drvdata);
562 cc_req_mgr_fini(new_drvdata);
564 cc_fips_fini(new_drvdata);
566 cc_debugfs_fini(new_drvdata);
568 fini_cc_regs(new_drvdata);
573 clk_disable_unprepare(new_drvdata->clk);