Lines Matching defs:ndev
42 static void clear_nps_core_err_intr(struct nitrox_device *ndev)
47 value = nitrox_read_csr(ndev, NPS_CORE_INT);
48 nitrox_write_csr(ndev, NPS_CORE_INT, value);
50 dev_err_ratelimited(DEV(ndev), "NSP_CORE_INT 0x%016llx\n", value);
53 static void clear_nps_pkt_err_intr(struct nitrox_device *ndev)
59 pkt_int.value = nitrox_read_csr(ndev, NPS_PKT_INT);
60 dev_err_ratelimited(DEV(ndev), "NPS_PKT_INT 0x%016llx\n",
65 value = nitrox_read_csr(ndev, offset);
66 nitrox_write_csr(ndev, offset, value);
67 dev_err_ratelimited(DEV(ndev),
71 value = nitrox_read_csr(ndev, offset);
72 nitrox_write_csr(ndev, offset, value);
75 enable_pkt_solicit_port(ndev, i);
77 dev_err_ratelimited(DEV(ndev),
81 value = nitrox_read_csr(ndev, offset);
82 nitrox_write_csr(ndev, offset, value);
83 dev_err_ratelimited(DEV(ndev),
89 value = nitrox_read_csr(ndev, offset);
90 nitrox_write_csr(ndev, offset, value);
91 dev_err_ratelimited(DEV(ndev),
94 value = nitrox_read_csr(ndev, offset);
95 nitrox_write_csr(ndev, offset, value);
98 enable_pkt_input_ring(ndev, i);
100 dev_err_ratelimited(DEV(ndev),
104 value = nitrox_read_csr(ndev, offset);
105 nitrox_write_csr(ndev, offset, value);
106 dev_err_ratelimited(DEV(ndev),
111 static void clear_pom_err_intr(struct nitrox_device *ndev)
115 value = nitrox_read_csr(ndev, POM_INT);
116 nitrox_write_csr(ndev, POM_INT, value);
117 dev_err_ratelimited(DEV(ndev), "POM_INT 0x%016llx\n", value);
120 static void clear_pem_err_intr(struct nitrox_device *ndev)
124 value = nitrox_read_csr(ndev, PEM0_INT);
125 nitrox_write_csr(ndev, PEM0_INT, value);
126 dev_err_ratelimited(DEV(ndev), "PEM(0)_INT 0x%016llx\n", value);
129 static void clear_lbc_err_intr(struct nitrox_device *ndev)
135 lbc_int.value = nitrox_read_csr(ndev, LBC_INT);
136 dev_err_ratelimited(DEV(ndev), "LBC_INT 0x%016llx\n", lbc_int.value);
141 value = nitrox_read_csr(ndev, offset);
142 nitrox_write_csr(ndev, offset, value);
144 value = nitrox_read_csr(ndev, offset);
145 nitrox_write_csr(ndev, offset, value);
150 dev_err_ratelimited(DEV(ndev), "CAM_SOFT_ERR, invalidating LBC\n");
151 invalidate_lbc(ndev);
156 value = nitrox_read_csr(ndev, offset);
157 nitrox_write_csr(ndev, offset, value);
159 value = nitrox_read_csr(ndev, offset);
160 nitrox_write_csr(ndev, offset, value);
165 value = nitrox_read_csr(ndev, offset);
166 nitrox_write_csr(ndev, offset, value);
168 value = nitrox_read_csr(ndev, offset);
169 nitrox_write_csr(ndev, offset, value);
171 nitrox_write_csr(ndev, LBC_INT, lbc_int.value);
174 static void clear_efl_err_intr(struct nitrox_device *ndev)
183 core_int.value = nitrox_read_csr(ndev, offset);
184 nitrox_write_csr(ndev, offset, core_int.value);
185 dev_err_ratelimited(DEV(ndev), "ELF_CORE(%d)_INT 0x%016llx\n",
189 value = nitrox_read_csr(ndev, offset);
190 nitrox_write_csr(ndev, offset, value);
195 static void clear_bmi_err_intr(struct nitrox_device *ndev)
199 value = nitrox_read_csr(ndev, BMI_INT);
200 nitrox_write_csr(ndev, BMI_INT, value);
201 dev_err_ratelimited(DEV(ndev), "BMI_INT 0x%016llx\n", value);
207 struct nitrox_device *ndev = qvec->ndev;
210 if (ndev->mode == __NDEV_MODE_PF) {
226 struct nitrox_device *ndev = qvec->ndev;
229 core_int.value = nitrox_read_csr(ndev, NPS_CORE_INT_ACTIVE);
232 clear_nps_core_err_intr(ndev);
235 clear_nps_pkt_err_intr(ndev);
238 clear_pom_err_intr(ndev);
241 clear_pem_err_intr(ndev);
244 clear_lbc_err_intr(ndev);
247 clear_efl_err_intr(ndev);
250 clear_bmi_err_intr(ndev);
254 nitrox_pf2vf_mbox_handler(ndev);
258 nitrox_write_csr(ndev, NPS_CORE_INT_ACTIVE, core_int.value);
263 void nitrox_unregister_interrupts(struct nitrox_device *ndev)
265 struct pci_dev *pdev = ndev->pdev;
268 for (i = 0; i < ndev->num_vecs; i++) {
272 qvec = ndev->qvec + i;
285 kfree(ndev->qvec);
286 ndev->qvec = NULL;
290 int nitrox_register_interrupts(struct nitrox_device *ndev)
292 struct pci_dev *pdev = ndev->pdev;
311 dev_err(DEV(ndev), "Error in getting vec count %d\n", nr_vecs);
318 dev_err(DEV(ndev), "msix vectors %d alloc failed\n", nr_vecs);
321 ndev->num_vecs = nr_vecs;
323 ndev->qvec = kcalloc(nr_vecs, sizeof(*qvec), GFP_KERNEL);
324 if (!ndev->qvec) {
331 qvec = &ndev->qvec[i];
334 if (qvec->ring >= ndev->nr_queues)
337 qvec->cmdq = &ndev->pkt_inq[qvec->ring];
343 dev_err(DEV(ndev), "irq failed for pkt ring/port%d\n",
357 qvec = &ndev->qvec[i];
358 qvec->ndev = ndev;
365 dev_err(DEV(ndev), "irq failed for nitrox-core-int%d\n", i);
378 nitrox_unregister_interrupts(ndev);
382 void nitrox_sriov_unregister_interrupts(struct nitrox_device *ndev)
384 struct pci_dev *pdev = ndev->pdev;
387 for (i = 0; i < ndev->num_vecs; i++) {
391 qvec = ndev->qvec + i;
395 vec = ndev->iov.msix.vector;
403 kfree(ndev->qvec);
404 ndev->qvec = NULL;
408 int nitrox_sriov_register_interupts(struct nitrox_device *ndev)
410 struct pci_dev *pdev = ndev->pdev;
419 ndev->iov.msix.entry = NON_RING_MSIX_BASE;
420 ret = pci_enable_msix_exact(pdev, &ndev->iov.msix, NR_NON_RING_VECTORS);
422 dev_err(DEV(ndev), "failed to allocate nps-core-int%d\n",
432 qvec->ndev = ndev;
434 ndev->qvec = qvec;
435 ndev->num_vecs = NR_NON_RING_VECTORS;
439 vec = ndev->iov.msix.vector;
442 dev_err(DEV(ndev), "irq failed for nitrox-core-int%d\n",
456 nitrox_sriov_unregister_interrupts(ndev);