Lines Matching refs:ndev
13 * @ndev: NITROX device
15 static void emu_enable_cores(struct nitrox_device *ndev)
31 nitrox_write_csr(ndev, EMU_AE_ENABLEX(i), emu_ae.value);
32 nitrox_write_csr(ndev, EMU_SE_ENABLEX(i), emu_se.value);
38 * @ndev: NITROX device
40 void nitrox_config_emu_unit(struct nitrox_device *ndev)
48 emu_enable_cores(ndev);
59 nitrox_write_csr(ndev, offset, emu_wd_int.value);
61 nitrox_write_csr(ndev, offset, emu_ge_int.value);
65 static void reset_pkt_input_ring(struct nitrox_device *ndev, int ring)
74 pkt_in_ctl.value = nitrox_read_csr(ndev, offset);
76 nitrox_write_csr(ndev, offset, pkt_in_ctl.value);
81 pkt_in_ctl.value = nitrox_read_csr(ndev, offset);
89 pkt_in_cnts.value = nitrox_read_csr(ndev, offset);
90 nitrox_write_csr(ndev, offset, pkt_in_cnts.value);
94 void enable_pkt_input_ring(struct nitrox_device *ndev, int ring)
102 pkt_in_ctl.value = nitrox_read_csr(ndev, offset);
105 nitrox_write_csr(ndev, offset, pkt_in_ctl.value);
109 pkt_in_ctl.value = nitrox_read_csr(ndev, offset);
118 * @ndev: NITROX device
120 void nitrox_config_pkt_input_rings(struct nitrox_device *ndev)
124 for (i = 0; i < ndev->nr_queues; i++) {
125 struct nitrox_cmdq *cmdq = &ndev->pkt_inq[i];
130 reset_pkt_input_ring(ndev, i);
138 nitrox_write_csr(ndev, offset, cmdq->dma);
143 pkt_in_rsize.s.rsize = ndev->qlen;
144 nitrox_write_csr(ndev, offset, pkt_in_rsize.value);
148 nitrox_write_csr(ndev, offset, 0xffffffff);
154 nitrox_write_csr(ndev, offset, pkt_in_dbell.value);
157 enable_pkt_input_ring(ndev, i);
161 static void reset_pkt_solicit_port(struct nitrox_device *ndev, int port)
170 pkt_slc_ctl.value = nitrox_read_csr(ndev, offset);
172 nitrox_write_csr(ndev, offset, pkt_slc_ctl.value);
178 pkt_slc_ctl.value = nitrox_read_csr(ndev, offset);
186 pkt_slc_cnts.value = nitrox_read_csr(ndev, offset);
187 nitrox_write_csr(ndev, offset, pkt_slc_cnts.value);
191 void enable_pkt_solicit_port(struct nitrox_device *ndev, int port)
207 nitrox_write_csr(ndev, offset, pkt_slc_ctl.value);
211 pkt_slc_ctl.value = nitrox_read_csr(ndev, offset);
218 static void config_pkt_solicit_port(struct nitrox_device *ndev, int port)
223 reset_pkt_solicit_port(ndev, port);
230 nitrox_write_csr(ndev, offset, pkt_slc_int.value);
233 enable_pkt_solicit_port(ndev, port);
236 void nitrox_config_pkt_solicit_ports(struct nitrox_device *ndev)
240 for (i = 0; i < ndev->nr_queues; i++)
241 config_pkt_solicit_port(ndev, i);
246 * @ndev: NITROX device.
250 static void enable_nps_core_interrupts(struct nitrox_device *ndev)
261 nitrox_write_csr(ndev, NPS_CORE_INT_ENA_W1S, core_int.value);
264 void nitrox_config_nps_core_unit(struct nitrox_device *ndev)
269 nitrox_write_csr(ndev, NPS_CORE_CONTROL, 1ULL);
275 nitrox_write_csr(ndev, NPS_CORE_GBL_VFCFG, core_gbl_vfcfg.value);
278 enable_nps_core_interrupts(ndev);
283 * @ndev: NITROX device.
287 static void enable_nps_pkt_interrupts(struct nitrox_device *ndev)
290 nitrox_write_csr(ndev, NPS_PKT_IN_RERR_LO_ENA_W1S, (~0ULL));
291 nitrox_write_csr(ndev, NPS_PKT_IN_RERR_HI_ENA_W1S, (~0ULL));
292 nitrox_write_csr(ndev, NPS_PKT_IN_ERR_TYPE_ENA_W1S, (~0ULL));
294 nitrox_write_csr(ndev, NPS_PKT_SLC_RERR_HI_ENA_W1S, (~0ULL));
295 nitrox_write_csr(ndev, NPS_PKT_SLC_RERR_LO_ENA_W1S, (~0ULL));
296 nitrox_write_csr(ndev, NPS_PKT_SLC_ERR_TYPE_ENA_W1S, (~0uLL));
299 void nitrox_config_nps_pkt_unit(struct nitrox_device *ndev)
302 nitrox_config_pkt_input_rings(ndev);
303 nitrox_config_pkt_solicit_ports(ndev);
306 enable_nps_pkt_interrupts(ndev);
309 static void reset_aqm_ring(struct nitrox_device *ndev, int ring)
321 nitrox_write_csr(ndev, offset, aqmq_en_reg.value);
327 activity_stat.value = nitrox_read_csr(ndev, offset);
335 cmp_cnt.value = nitrox_read_csr(ndev, offset);
336 nitrox_write_csr(ndev, offset, cmp_cnt.value);
340 void enable_aqm_ring(struct nitrox_device *ndev, int ring)
348 nitrox_write_csr(ndev, offset, aqmq_en_reg.value);
352 void nitrox_config_aqm_rings(struct nitrox_device *ndev)
356 for (ring = 0; ring < ndev->nr_queues; ring++) {
357 struct nitrox_cmdq *cmdq = ndev->aqmq[ring];
364 reset_aqm_ring(ndev, ring);
370 nitrox_write_csr(ndev, offset, drbl.value);
376 nitrox_write_csr(ndev, offset, 0ULL);
380 nitrox_write_csr(ndev, offset, cmdq->dma);
385 qsize.host_queue_size = ndev->qlen;
386 nitrox_write_csr(ndev, offset, qsize.value);
392 nitrox_write_csr(ndev, offset, cmp_thr.value);
395 enable_aqm_ring(ndev, ring);
399 static void enable_aqm_interrupts(struct nitrox_device *ndev)
402 nitrox_write_csr(ndev, AQM_DBELL_OVF_LO_ENA_W1S, (~0ULL));
403 nitrox_write_csr(ndev, AQM_DBELL_OVF_HI_ENA_W1S, (~0ULL));
404 nitrox_write_csr(ndev, AQM_DMA_RD_ERR_LO_ENA_W1S, (~0ULL));
405 nitrox_write_csr(ndev, AQM_DMA_RD_ERR_HI_ENA_W1S, (~0ULL));
406 nitrox_write_csr(ndev, AQM_EXEC_NA_LO_ENA_W1S, (~0ULL));
407 nitrox_write_csr(ndev, AQM_EXEC_NA_HI_ENA_W1S, (~0ULL));
408 nitrox_write_csr(ndev, AQM_EXEC_ERR_LO_ENA_W1S, (~0ULL));
409 nitrox_write_csr(ndev, AQM_EXEC_ERR_HI_ENA_W1S, (~0ULL));
412 void nitrox_config_aqm_unit(struct nitrox_device *ndev)
415 nitrox_config_aqm_rings(ndev);
418 enable_aqm_interrupts(ndev);
421 void nitrox_config_pom_unit(struct nitrox_device *ndev)
429 nitrox_write_csr(ndev, POM_INT_ENA_W1S, pom_int.value);
432 for (i = 0; i < ndev->hw.se_cores; i++)
433 nitrox_write_csr(ndev, POM_PERF_CTL, BIT_ULL(i));
438 * @ndev: NITROX device
440 void nitrox_config_rand_unit(struct nitrox_device *ndev)
446 efl_rnm_ctl.value = nitrox_read_csr(ndev, offset);
449 nitrox_write_csr(ndev, offset, efl_rnm_ctl.value);
452 void nitrox_config_efl_unit(struct nitrox_device *ndev)
466 nitrox_write_csr(ndev, offset, efl_core_int.value);
469 nitrox_write_csr(ndev, offset, (~0ULL));
471 nitrox_write_csr(ndev, offset, (~0ULL));
475 void nitrox_config_bmi_unit(struct nitrox_device *ndev)
483 bmi_ctl.value = nitrox_read_csr(ndev, offset);
487 nitrox_write_csr(ndev, offset, bmi_ctl.value);
495 nitrox_write_csr(ndev, offset, bmi_int_ena.value);
498 void nitrox_config_bmo_unit(struct nitrox_device *ndev)
505 bmo_ctl2.value = nitrox_read_csr(ndev, offset);
507 nitrox_write_csr(ndev, offset, bmo_ctl2.value);
510 void invalidate_lbc(struct nitrox_device *ndev)
519 lbc_ctl.value = nitrox_read_csr(ndev, offset);
521 nitrox_write_csr(ndev, offset, lbc_ctl.value);
525 lbc_stat.value = nitrox_read_csr(ndev, offset);
532 void nitrox_config_lbc_unit(struct nitrox_device *ndev)
537 invalidate_lbc(ndev);
546 nitrox_write_csr(ndev, offset, lbc_int_ena.value);
549 nitrox_write_csr(ndev, offset, (~0ULL));
551 nitrox_write_csr(ndev, offset, (~0ULL));
554 nitrox_write_csr(ndev, offset, (~0ULL));
556 nitrox_write_csr(ndev, offset, (~0ULL));
559 void config_nps_core_vfcfg_mode(struct nitrox_device *ndev, enum vf_mode mode)
563 vfcfg.value = nitrox_read_csr(ndev, NPS_CORE_GBL_VFCFG);
566 nitrox_write_csr(ndev, NPS_CORE_GBL_VFCFG, vfcfg.value);
608 void nitrox_get_hwinfo(struct nitrox_device *ndev)
619 rst_boot.value = nitrox_read_csr(ndev, offset);
620 ndev->hw.freq = (rst_boot.pnr_mul + 3) * PLL_REF_CLK;
624 emu_fuse.value = nitrox_read_csr(ndev, offset);
627 ndev->hw.ae_cores += AE_CORES_PER_CLUSTER - dead_cores;
629 ndev->hw.se_cores += SE_CORES_PER_CLUSTER - dead_cores;
634 fus_dat1.value = nitrox_read_csr(ndev, offset);
637 ndev->hw.zip_cores = ZIP_MAX_CORES - dead_cores;
644 get_core_option(ndev->hw.se_cores, ndev->hw.ae_cores),
645 ndev->hw.freq,
646 get_feature_option(ndev->hw.zip_cores, ndev->hw.freq),
647 ndev->hw.revision_id);
650 strncpy(ndev->hw.partname, name, sizeof(ndev->hw.partname));
653 void enable_pf2vf_mbox_interrupts(struct nitrox_device *ndev)
660 nitrox_write_csr(ndev, reg_addr, value);
664 nitrox_write_csr(ndev, reg_addr, value);
667 void disable_pf2vf_mbox_interrupts(struct nitrox_device *ndev)
674 nitrox_write_csr(ndev, reg_addr, value);
678 nitrox_write_csr(ndev, reg_addr, value);