Lines Matching refs:offset
44 u64 offset;
58 offset = EMU_WD_INT_ENA_W1SX(i);
59 nitrox_write_csr(ndev, offset, emu_wd_int.value);
60 offset = EMU_GE_INT_ENA_W1SX(i);
61 nitrox_write_csr(ndev, offset, emu_ge_int.value);
70 u64 offset;
73 offset = NPS_PKT_IN_INSTR_CTLX(ring);
74 pkt_in_ctl.value = nitrox_read_csr(ndev, offset);
76 nitrox_write_csr(ndev, offset, pkt_in_ctl.value);
81 pkt_in_ctl.value = nitrox_read_csr(ndev, offset);
88 offset = NPS_PKT_IN_DONE_CNTSX(ring);
89 pkt_in_cnts.value = nitrox_read_csr(ndev, offset);
90 nitrox_write_csr(ndev, offset, pkt_in_cnts.value);
98 u64 offset;
101 offset = NPS_PKT_IN_INSTR_CTLX(ring);
102 pkt_in_ctl.value = nitrox_read_csr(ndev, offset);
105 nitrox_write_csr(ndev, offset, pkt_in_ctl.value);
109 pkt_in_ctl.value = nitrox_read_csr(ndev, offset);
128 u64 offset;
137 offset = NPS_PKT_IN_INSTR_BADDRX(i);
138 nitrox_write_csr(ndev, offset, cmdq->dma);
141 offset = NPS_PKT_IN_INSTR_RSIZEX(i);
144 nitrox_write_csr(ndev, offset, pkt_in_rsize.value);
147 offset = NPS_PKT_IN_INT_LEVELSX(i);
148 nitrox_write_csr(ndev, offset, 0xffffffff);
151 offset = NPS_PKT_IN_INSTR_BAOFF_DBELLX(i);
154 nitrox_write_csr(ndev, offset, pkt_in_dbell.value);
166 u64 offset;
169 offset = NPS_PKT_SLC_CTLX(port);
170 pkt_slc_ctl.value = nitrox_read_csr(ndev, offset);
172 nitrox_write_csr(ndev, offset, pkt_slc_ctl.value);
178 pkt_slc_ctl.value = nitrox_read_csr(ndev, offset);
185 offset = NPS_PKT_SLC_CNTSX(port);
186 pkt_slc_cnts.value = nitrox_read_csr(ndev, offset);
187 nitrox_write_csr(ndev, offset, pkt_slc_cnts.value);
195 u64 offset;
197 offset = NPS_PKT_SLC_CTLX(port);
207 nitrox_write_csr(ndev, offset, pkt_slc_ctl.value);
211 pkt_slc_ctl.value = nitrox_read_csr(ndev, offset);
221 u64 offset;
226 offset = NPS_PKT_SLC_INT_LEVELSX(port);
230 nitrox_write_csr(ndev, offset, pkt_slc_int.value);
315 u64 offset;
318 offset = AQMQ_ENX(ring);
321 nitrox_write_csr(ndev, offset, aqmq_en_reg.value);
325 offset = AQMQ_ACTIVITY_STATX(ring);
327 activity_stat.value = nitrox_read_csr(ndev, offset);
334 offset = AQMQ_CMP_CNTX(ring);
335 cmp_cnt.value = nitrox_read_csr(ndev, offset);
336 nitrox_write_csr(ndev, offset, cmp_cnt.value);
343 u64 offset;
345 offset = AQMQ_ENX(ring);
348 nitrox_write_csr(ndev, offset, aqmq_en_reg.value);
361 u64 offset;
367 offset = AQMQ_DRBLX(ring);
370 nitrox_write_csr(ndev, offset, drbl.value);
375 offset = AQMQ_NXT_CMDX(ring);
376 nitrox_write_csr(ndev, offset, 0ULL);
379 offset = AQMQ_BADRX(ring);
380 nitrox_write_csr(ndev, offset, cmdq->dma);
383 offset = AQMQ_QSZX(ring);
386 nitrox_write_csr(ndev, offset, qsize.value);
389 offset = AQMQ_CMP_THRX(ring);
392 nitrox_write_csr(ndev, offset, cmp_thr.value);
443 u64 offset;
445 offset = EFL_RNM_CTL_STATUS;
446 efl_rnm_ctl.value = nitrox_read_csr(ndev, offset);
449 nitrox_write_csr(ndev, offset, efl_rnm_ctl.value);
458 u64 offset;
461 offset = EFL_CORE_INT_ENA_W1SX(i);
466 nitrox_write_csr(ndev, offset, efl_core_int.value);
468 offset = EFL_CORE_VF_ERR_INT0_ENA_W1SX(i);
469 nitrox_write_csr(ndev, offset, (~0ULL));
470 offset = EFL_CORE_VF_ERR_INT1_ENA_W1SX(i);
471 nitrox_write_csr(ndev, offset, (~0ULL));
479 u64 offset;
482 offset = BMI_CTL;
483 bmi_ctl.value = nitrox_read_csr(ndev, offset);
487 nitrox_write_csr(ndev, offset, bmi_ctl.value);
490 offset = BMI_INT_ENA_W1S;
495 nitrox_write_csr(ndev, offset, bmi_int_ena.value);
501 u64 offset;
504 offset = BMO_CTL2;
505 bmo_ctl2.value = nitrox_read_csr(ndev, offset);
507 nitrox_write_csr(ndev, offset, bmo_ctl2.value);
515 u64 offset;
518 offset = LBC_INVAL_CTL;
519 lbc_ctl.value = nitrox_read_csr(ndev, offset);
521 nitrox_write_csr(ndev, offset, lbc_ctl.value);
523 offset = LBC_INVAL_STATUS;
525 lbc_stat.value = nitrox_read_csr(ndev, offset);
535 u64 offset;
540 offset = LBC_INT_ENA_W1S;
546 nitrox_write_csr(ndev, offset, lbc_int_ena.value);
548 offset = LBC_PLM_VF1_64_INT_ENA_W1S;
549 nitrox_write_csr(ndev, offset, (~0ULL));
550 offset = LBC_PLM_VF65_128_INT_ENA_W1S;
551 nitrox_write_csr(ndev, offset, (~0ULL));
553 offset = LBC_ELM_VF1_64_INT_ENA_W1S;
554 nitrox_write_csr(ndev, offset, (~0ULL));
555 offset = LBC_ELM_VF65_128_INT_ENA_W1S;
556 nitrox_write_csr(ndev, offset, (~0ULL));
615 u64 offset;
618 offset = RST_BOOT;
619 rst_boot.value = nitrox_read_csr(ndev, offset);
623 offset = EMU_FUSE_MAPX(i);
624 emu_fuse.value = nitrox_read_csr(ndev, offset);
633 offset = FUS_DAT1;
634 fus_dat1.value = nitrox_read_csr(ndev, offset);