Lines Matching refs:ctrl
22 #include "ctrl.h"
106 struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
119 clrsetbits_32(&ctrl->deco_rsr, 0, DECORSR_JR0);
121 while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) &&
128 clrsetbits_32(&ctrl->deco_rq, 0, DECORR_RQD0ENABLE);
130 while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0) &&
136 clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
180 clrsetbits_32(&ctrl->deco_rsr, DECORSR_JR0, 0);
183 clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
281 struct caam_ctrl __iomem *ctrl;
285 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
333 rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_MASK;
360 struct caam_ctrl __iomem *ctrl;
364 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
365 r4tst = &ctrl->r4tst[0];
642 struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
651 (struct caam_perfmon __iomem *)&ctrl->perfmon;
660 (struct version_regs __iomem *)&ctrl->vreg;
673 rd_reg32(&ctrl->r4tst[0].rdsta);
684 rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_MASK;
738 clrsetbits_32(&ctrl->scfgr, 0, SCFGR_RDBENABLE);
758 struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
762 state->mcr = rd_reg32(&ctrl->mcr);
763 state->scfgr = rd_reg32(&ctrl->scfgr);
765 deco_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) &
769 rd_reg32(&ctrl->deco_mid[i].liodn_ms);
771 rd_reg32(&ctrl->deco_mid[i].liodn_ls);
774 jr_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) &
778 rd_reg32(&ctrl->jr_mid[i].liodn_ms);
780 rd_reg32(&ctrl->jr_mid[i].liodn_ls);
788 struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
792 wr_reg32(&ctrl->mcr, state->mcr);
793 wr_reg32(&ctrl->scfgr, state->scfgr);
795 deco_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) &
798 wr_reg32(&ctrl->deco_mid[i].liodn_ms,
800 wr_reg32(&ctrl->deco_mid[i].liodn_ls,
804 jr_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) &
807 wr_reg32(&ctrl->jr_mid[i].liodn_ms,
809 wr_reg32(&ctrl->jr_mid[i].liodn_ls,
814 clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START |
855 struct caam_ctrl __iomem *ctrl;
905 ctrl = devm_of_iomap(dev, nprop, 0, NULL);
906 ret = PTR_ERR_OR_ZERO(ctrl);
925 ((__force uint8_t *)ctrl + reg);
937 (struct caam_perfmon __iomem *)&ctrl->perfmon;
943 rd_reg32(&ctrl->mcr) & MCFGR_LONG_PTR)
980 ctrlpriv->ctrl = (struct caam_ctrl __iomem __force *)ctrl;
982 ((__force uint8_t *)ctrl +
986 ((__force uint8_t *)ctrl +
1019 clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK,
1023 handle_imx6_err005766(&ctrl->mcr);
1029 scfgr = rd_reg32(&ctrl->scfgr);
1047 clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START |
1074 ((__force uint8_t *)ctrl +
1110 (struct version_regs __iomem *)&ctrl->vreg;