Lines Matching defs:spu2_mode
92 enum spu2_cipher_mode *spu2_mode)
96 *spu2_mode = SPU2_CIPHER_MODE_ECB;
99 *spu2_mode = SPU2_CIPHER_MODE_CBC;
102 *spu2_mode = SPU2_CIPHER_MODE_OFB;
105 *spu2_mode = SPU2_CIPHER_MODE_CFB;
108 *spu2_mode = SPU2_CIPHER_MODE_CTR;
111 *spu2_mode = SPU2_CIPHER_MODE_CCM;
114 *spu2_mode = SPU2_CIPHER_MODE_GCM;
117 *spu2_mode = SPU2_CIPHER_MODE_XTS;
132 * @spu2_mode: [out] cipher mode value used by spu2 hardware
140 enum spu2_cipher_mode *spu2_mode)
144 err = spu2_cipher_mode_xlate(cipher_mode, spu2_mode);
197 enum spu2_hash_mode *spu2_mode)
201 *spu2_mode = SPU2_HASH_MODE_XCBC_MAC;
204 *spu2_mode = SPU2_HASH_MODE_CMAC;
207 *spu2_mode = SPU2_HASH_MODE_HMAC;
210 *spu2_mode = SPU2_HASH_MODE_CCM;
213 *spu2_mode = SPU2_HASH_MODE_GCM;
229 * @spu2_mode: [out] hash mode value used by SPU2 hardware
236 enum spu2_hash_type *spu2_type, enum spu2_hash_mode *spu2_mode)
240 err = spu2_hash_mode_xlate(hash_mode, spu2_mode);
548 * @spu2_mode: Cipher mode
556 enum spu2_cipher_mode spu2_mode,
569 (spu2_mode << SPU2_CIPH_MODE_SHIFT);
1131 enum spu2_cipher_mode spu2_mode;
1143 cipher_parms->type, &spu2_type, &spu2_mode);
1149 spu2_ciph_mode_name(spu2_mode));
1153 err = spu2_fmd_init(fmd, spu2_type, spu2_mode, cipher_parms->key_len,