Lines Matching refs:value
95 * @busy_scaled: Scaled busy value which is used to calculate next
172 * based on the MSR_IA32_MISC_ENABLE value and whether or
175 * @turbo_disabled_mf: The @turbo_disabled value reflected by cpuinfo.max_freq.
192 * @policy: CPUFreq policy value
201 * @prev_aperf: Last APERF value read from APERF MSR
202 * @prev_mperf: Last MPERF value read from MPERF MSR
203 * @prev_tsc: Last timestamp counter (TSC) value
217 * @epp_cached Cached HWP energy-performance preference value
218 * @hwp_req_cached: Cached value of the last HWP Request MSR
219 * @hwp_cap_cached: Cached value of the last HWP Capabilities MSR
277 * @get_val: Callback to convert P state to actual MSR write value
458 * Check if the control value in _PSS is for PERF_CTL MSR, which should
590 * Cast the min P-state value retrieved via pstate_funcs.get_min() to
738 * The EPB is a 4 bit value, but our ranges restrict the
739 * value which can be set. Here only using top two bits
753 * Use the cached HWP Request MSR value, because in the active mode the
757 u64 value = READ_ONCE(cpu->hwp_req_cached);
759 value &= ~GENMASK_ULL(31, 24);
760 value |= (u64)epp << 24;
766 WRITE_ONCE(cpu->hwp_req_cached, value);
767 ret = wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
973 u64 value;
982 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
984 value &= ~HWP_MIN_PERF(~0L);
985 value |= HWP_MIN_PERF(min);
987 value &= ~HWP_MAX_PERF(~0L);
988 value |= HWP_MAX_PERF(max);
996 epp = intel_pstate_get_epp(cpu_data, value);
1004 /* skip setting EPP, when saved value is invalid */
1015 epp = intel_pstate_get_epp(cpu_data, value);
1022 value &= ~GENMASK_ULL(31, 24);
1023 value |= (u64)epp << 24;
1028 WRITE_ONCE(cpu_data->hwp_req_cached, value);
1029 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
1036 u64 value = READ_ONCE(cpu->hwp_req_cached);
1045 * temporary value with the cached EPP one.
1047 value &= ~GENMASK_ULL(31, 24);
1048 value |= HWP_ENERGY_PERF_PREFERENCE(cpu->epp_cached);
1058 * Clear the desired perf field in the cached HWP request value to
1062 value &= ~HWP_DESIRED_PERF(~0L);
1063 WRITE_ONCE(cpu->hwp_req_cached, value);
1065 value &= ~GENMASK_ULL(31, 0);
1069 value |= HWP_MAX_PERF(min_perf);
1070 value |= HWP_MIN_PERF(min_perf);
1074 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE);
1076 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
1644 u64 value;
1649 rdmsrl_safe(MSR_HWP_STATUS, &value);
1650 if (!(value & 0x01))
1743 * Use hard coded value per gen to update the balance_perf
1768 u64 value;
1770 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1771 return (value >> 8) & 0x7F;
1776 u64 value;
1778 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1779 return (value >> 16) & 0x7F;
1784 u64 value;
1786 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
1787 return value & 0x7F;
1815 u64 value;
1821 rdmsrl(MSR_FSB_FREQ, value);
1822 i = value & 0x7;
1830 u64 value;
1837 rdmsrl(MSR_FSB_FREQ, value);
1838 i = value & 0xF;
1846 u64 value;
1848 rdmsrl(MSR_ATOM_CORE_VIDS, value);
1849 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1850 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1856 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
1857 cpudata->vid.turbo = value & 0x7f;
1862 u64 value;
1864 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value);
1865 return (value >> 40) & 0xFF;
1870 u64 value;
1872 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value);
1873 return (value >> 8) & 0xFF;
1946 u64 value;
1949 rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value);
1951 ret = (value) & 255;
1975 u64 value;
1978 rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value);
1980 ret = (((value) >> 8) & 0xFF);
2638 * is used as a stale frequency value. So, keep it within limits.
2784 * Set the policy to powersave to provide a valid fallback value in case
2863 u64 prev = READ_ONCE(cpu->hwp_req_cached), value = prev;
2865 value &= ~HWP_MIN_PERF(~0L);
2866 value |= HWP_MIN_PERF(min);
2868 value &= ~HWP_MAX_PERF(~0L);
2869 value |= HWP_MAX_PERF(max);
2871 value &= ~HWP_DESIRED_PERF(~0L);
2872 value |= HWP_DESIRED_PERF(desired);
2874 if (value == prev)
2877 WRITE_ONCE(cpu->hwp_req_cached, value);
2879 wrmsrl(MSR_HWP_REQUEST, value);
2881 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
3033 u64 value;
3039 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value);
3040 WRITE_ONCE(cpu->hwp_req_cached, value);
3042 cpu->epp_cached = intel_pstate_get_epp(cpu, value);
3098 u64 value = READ_ONCE(cpu->hwp_req_cached);
3102 * intel_cpufreq_adjust_perf() is in use and the last value
3105 value &= ~HWP_DESIRED_PERF(~0L);
3106 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
3107 WRITE_ONCE(cpu->hwp_req_cached, value);
3404 u64 value;
3406 rdmsrl(MSR_PM_ENABLE, value);
3407 return !!(value & 0x1);
3412 * Set EPP value as 102, this is the max suggested EPP